Anritsu MS9710C - Definition of ERROR Event Status Register Bits

8-17
8.5 Extended Event Status Register
8.5.2 Definition of ERROR event status register bits
This section explains ERROR event status register model operation and names
and meanings of event bits.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
&
&
&
&
&
&
&
&
Logical OR
ESB summary message bit
(to Status Byte register bit 3)
Not used
Not used
Not used
Not used
Not used
Not used
Peak / Dip
RES-Uncal
ERROR event status registerERROR event status enable register
Read by ESR3?
Set with ESE3<NRf>.
Read with ESE3?.
disabled=0, enabled=128 (2
7
)
disabled=0, enabled=64 (2
6
)
disabled=0, enabled=32 (2
5
)
disabled=0, enabled=16 (2
4
)
disabled=0, enabled=8 (2
3
)
disabled=0, enabled=4 (2
2
)
disabled=0, enabled=2 (2
1
)
disabled=0, enabled=1 (2
0
)
Description






Occurrenceofpeak/dipdetectionerror
OccurrenceofRES-Uncalerror
Event name
Notused
Notused
Notused
Notused
Notused
Notused
Peak/DipError
RES-Uncal
Bit
7
6
5
4
3
2
1
0