Anritsu MS9710C - Extended Event Status Register

8-15
8.5 Extended Event Status Register
Devices conforming to IEEE 488.2 require register models for status byte and
standard event status registers including an enable register.
IEEE 488.2 assigns status byte register bit 7 (DIO 8) and bits 3 (DIO 4) to 0 (DIO
1) to the status summary bits transferred from an extended register model and
extended queue model.
As shown below, the MS9710C does not use bits 7, 1, and 0. It assigns bits 3 and
2 to END and ERROR summary bits for status summary bits transferred from the
extended register model.
Not used
ESB
MAV
3
2
1
Not used
MSS 6 RQS
Standard event
register
Status summary
message
Status Byte Register
……Output Queue
END event
register model
Not used
Occurrence of
service request
ERROR event summary bit
MAV summary bit
Standard event summary bit
END event summary bit
Data Data Data Data Data
ERROR event
register model
Let’s take a look at definition, read, write, and clearing of END and ERROR
extended event register model bits.
8.5 Extended Event Status Register