Section 8 Status Structure
8-14
8.4.3 Reading, writing, and clearing the standard event status register
Read
Write
Clearing
This register is read destructively in response to the ∗ESR? common command. In other words,
this register is cleared after being read. The event bit assigned binary weights and converted to a
decimal value <NR1> is the response message.
This register cannot be written externally; however, it can be cleared.
This register is cleared in the following cases:
(1) A ∗CLS command is received.
(2) The power is turned on if the Power-ON status clear flag is True.
The device executing a Power-ON sequence first clears the standard event status register, then
records the events that have occurred in this sequence (e.g., PON event bit setting).
(3) An event is read in response to an ∗ESR? query command.
8.4.4 Reading, writing, and clearing the standard event status enable
register
Read
Write
Clearing
This register is read non-destructively in response to the ∗ESR? common command. In other
words, this register is not cleared after being read. The response message is assigned binary
weights, converted from a binary value to a decimal value <NR1>, and returned.
This register is written using an ∗ESS common command. Register bits 0 to 8 are assigned weights
1, 2, 4, 8, 16, 32, 64, and 128 respectively, so a total of values of the desired write data bits is sent
as <DECIMAL NUMERIC PROGRAM DATA>.
This register is cleared in the following cases:
(1) An ∗ESE command with its data value being 0 is received.
(2) The power is turned on with the Power-ON status clear flag in the True state or the power is
turned on when a ∗PSC command is not supported.
The standard event status register is not affected by the following:
(1) Change in the state of the IEEE 488.1-defined device clear function
(2) Reception of an ∗RST common command
(3) Reception of a ∗CLS common command
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