Section 8 Status Structure
8-8
(3) Definition of MSS (Master Summary Status)
The MSS indicates that the device has at least one cause of issuing a service
request. In the device’s response to the ∗STB? query, the MSS message
appears in bit 6. However, it does not appear in the response to serial poll-
ing. It must not be regarded as part of the IEEE 488.1 defined status byte.
The MSS is the result of ORing the values of STB register and SRQ enable
(SRE) register bits totally. Specifically, the MSS is defined as follows:
(STB Register bit 0 AND SRE Register bit 0)
OR
(STB Register bit 1 AND SRE Register bit 1)
OR
:
:
(STB Register bit 5 AND SRE Register bit 5)
OR
(STB Register bit 7 AND SRE Register bit 7)
In the definition of the MSS, the values of bits 6 of the STB register and
SQR enable register are ignored. Accordingly, when calculating the MSS
value, the status byte may be handled assuming that it is represented by 8
bits and bit 6 is always 0.
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