BL702/704/706 Reference Manual
Bits
Name Type Reset Description
21:16 FIFODACN R 6’d0 fifo data number
15 FIFORDYM R/W 1’b1 write 1 mask
14 FURM R/W 1’b0 write 1 mask
13 FORM R/W 1’b0 write 1 mask
12 RDYM R/W 1’b0 write 1 mask
11 RSVD
10 URCL W1C 1’b0 Write 1 to clear flag
9 ORCL W1C 1’b0 Write 1 to clear flag
8 RDYCLR W1C 1’b0 Write 1 to clear flag
7 FIFORDY R 1’b0 FIFO ready interrupt flag
6 FIFOUR R 1’b0 FIFO underrun interrupt flag
5 FIFOOR R 1’b0 FIFO overrun interrupt flag
4 RDY R 1’b0 Conversion data ready interrupt flag
3 FIFOFULL R 1’b0 FIFO full flag
2 FIFONE R 1’b0 FIFO not empty flag
1 FIFOCLR W1C 1’b0 FIFO clear signal
0 DMAEN R/W 1’b0 GPADC DMA enbale
4.4.2 gpadc_dma_rdata
Address:0x40002004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DMARDA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMARDA
Bits
Name Type Reset Description
31:26 RSVD
25:0 DMARDA R 26’d0 GPADC finial conversion result stored in the FIFO
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