Bouffalo Lab BL702 - Introduction; Reset and Clock; Reset Source

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Reset and clock
2.1 Introduction
The reset sources included in the chip: hardware reset, watchdog reset, software reset. The chip contains multiple
clock sources: XTAL, PLL, RC. It is allocated to each module through configuration such as frequency division.
2.2 Reset source
The reset sources are as follows:
• Hardware reset: reset via pin
– Pin power reset (PU_CHIP = 0-> 1): similar to power reset
– Power-on reset: the chip recovers from power failure, and HBN logic resets the chip system
• Watchdog reset
– When the watchdog alarm triggers the reset signal, the reset management unit will reset the chip system after
necessary preparations, and the internal logic of the watchdog will record the status of the watchdog reset
• Software reset: partial reset by software setting register
– Software initial reset (reg_ctrl_pwron_rst): trigger the rising edge of this register by software to reset the chip
system
– Software CPU reset (reg_ctrl_cpu_reset): Trigger the rising edge of this register by software to reset the CPU
part of the system
– Software system reset (reg_ctrl_sys_reset): Trigger the rising edge of this register by software, retain neces-
sary logic processing such as power management unit, and reset the chip part of the system
– Software module reset: Set software reset according to the needs of specific modules
BL702/704/706 Reference Manual
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