BL702/704/706 Reference Manual
11.3.1 Start and stop conditions
All transfers begin with a START condition and end with a STOP condition.
The start and stop conditions are generally generated by the master. The bus is considered to be in a busy state after
the start condition, and is considered to be in an idle state for a period of time after the stop condition.
Start condition: SDA generates a high-to-low level transition when SCL is high;
Stop condition: SDA generates a low-to-high level transition when SCL is high.
The waveform diagram is as follows:
SDA
SCL
S
START condition
P
STOP condition
Fig. 11.1: I2C stop/start condition
11.3.2 Data transmission format
The first 8 bits transmitted are the address byte, including the 7-bit slave address and the 1-bit direction bit. Data sent
or received by the host is controlled by the eighth bit of the first byte sent by the host.
If it is 0, it means that the data is sent by the master; if it is 1, it means that the data is received by the master, and
then the slave sends an acknowledge bit (ACK). After the data transmission is completed, the master sends a stop
signal. The waveform is as follows:
SDA
SCL
S
P
START
condition
STOP
condition
1-7 8 9
1-7 8 9 1-7 8
9
ADDRESS
R/W
ACK DATA ACK DATA ACK
Fig. 11.2: I2C data transmission format
Timing of master transmission and slave reception
BL702/704/706 Reference Manual 208/ 375
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