BL702/704/706 Reference Manual
Ethernet
Core
Host Interface
Tx Data
TX Ethernet MAC
Tx Control
Signals
Tx Control
Signals
Tx Control
Signals
Tx Control
Signals
Tx Control
Signals
MAC Control Module
(Flow control)
RX Ethernet MAC
MII Management
Modul
MAC
Ethernet PHY
Tx Data
Tx PHY
Control
Signals
Rx Data
Rx PHY
Control
Signals
bus
Management
Data
Ethernet
Fig. 17.1: EMAC architecture
The module’s control register can read and write the PHY register through MDIO to realize configuration, select mode
(half/full duplex), initiate negotiation and other operations.
The receiving module filters and checks the received data frame: whether there is a legal preamble, FCS, length, etc.
And according to the descriptor, the data frame is stored in the designated buffer address.
The sending module obtains data from the memory according to the data buffer descriptor, adds preamble, FCS, pad,
etc., and then sends the data according to the CSMA/CD protocol.
If CRS is detected, the retry will be delayed.
BL702/704/706 Reference Manual 291/ 375
@2021 Bouffalo Lab
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