Bouffalo Lab BL702 - LLI Architecture

BL702/704/706 Reference Manual
Source Address
Dest Address
Next LLI
DMA Control
Source Address
Dest Address
Next LLI
DMA Control
·
·
·
Source Address
Dest Address
Next LLI
DMA Control
IDLE
channel enable
IntTCEnable=
0
IntTCEnable=
0
IntTCEnable=
0
IntTCEnable=
1
Fig. 6.2: LLI architecture
6.3.5 DMA interrupt
• DMA_INT_TCOMPLETED
– Data transmission completed interrupt. When a data transmission is completed, this interrupt will be entered.
• DMA_INT_ERR
– Data transmission error interrupt, when an error occurs during data transmission, this interrupt will be entered
BL702/704/706 Reference Manual 124/ 375
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