Bouffalo Lab BL702 - Clk_Cfg1

BL702/704/706 Reference Manual
Bits
Name Type Reset Description
5:4 PLLSEL R/W 0 pll clock selection
0: 57.6MHz
1: 96MHz
2: 144MHz
3: 120MHz (Clock Freq will be changes with Audio PLL, not
sugges use this CLK)
3 BLCKEN R/W 1 bclk force on
2 HCLKEN R/W 1 hclk force on
1 FCLKEN R/W 1 fclk force on
0 PLLEN R/W 1 pll clock enable for fclk
3.3.2 clk_cfg1
Address：0x40000004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD MAC
ZBEN
BLE
EN
RSVD BLECLKSL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD I2S
CLK
I2S
CLEN
I2S
CSEL
RSVD USB
DIV
USB
CLK
QDEC
CSEL
RSVD QDECCDIV
Bits
Name Type Reset Description
31:26 RSVD
25 MACZBEN R/W 1 mac154 zigbee clock enable
24 BLEEN R/W 1 ble clock enable
23:22 RSVD
21:16 BLECLKSL R/W 6’d16 HW reserved ; for ble to generate 1us/0.5us tick pulse
15 RSVD
14 I2SCLK R/W 0 0 : no output reference clock on I2S_0 ref_clock port ; 1:
output reference clock on I2S_0 ref_clock port
13 I2SCLEN R/W 0 I2S0 Clock Enable
12 I2SCSEL R/W 0 I2S Clock Source Select. 0: Audio PLL, 1: reserved
11:10 RSVD
9 USBDIV R/W 1 USB Clock div2 from 96MHz
8 USBCLK R/W 1 USB Clock Enable
BL702/704/706 Reference Manual 41/ 375
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