Bouffalo Lab BL702 - Dig32 K_Wakeup_Ctrl; Gpadc_32 M_Src_Ctrl

BL702/704/706 Reference Manual
3.3.15 GPADC_32M_SRC_CTRL
Address：0x400000a4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD GADC
DIV
GADC
SEL
RSVD GADCDIV
Bits
Name Type Reset Description
31:9 RSVD
8 GADCDIV R/W 1 GPADC 32M Clock Dvider Enable
7 GADCSEL R/W 0 GPADC Clock Source Select. 0: Audio PLL, 1: xclk
6 RSVD
5:0 GADCDIV R/W 6’d2 GPADC 32M Clock Divider (gpadc clock)/(N+1)
3.3.16 DIG32K_WAKEUP_CTRL
Address：0x400000a8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD CLKSCSEL RSVD COMP 512K
EN
RSVD 512KDIV
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD 32K
COMP
32K
EN
RSVD 32KDIV
Bits
Name Type Reset Description
31:30 RSVD
29:28 CLKSCSEL R/W 0 0:PLL 32MHz 1:xclk 2:Audio PLL
27:26 RSVD
25 COMP R/W 1 Compensation => Duty of dig_512k_out = N : N+1
24 512KEN R/W 1 Enable dig_512k_out
23 RSVD
22:16 512KDIV R/W 7’d62 (PLL 32MHz or xclk) / dig_512k_div
Ex: Set 46 for 24MHz ; Set 62 for 32MHz ; Set 75 for
38.4MHz ; Set 78 for 40MHz
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