Bouffalo Lab BL702 - Cpu_Clk_Cfg; Seam_Misc

BL702/704/706 Reference Manual
3.3.13 seam_misc
Address：0x4000007c
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD EMSEL
Bits
Name Type Reset Description
31:4 RSVD
3:0 EMSEL R/W 4’h3 em/ocram share memory em select 0x0: 0KB ; 0x3:8KB ;
0xF:16KB
3.3.14 CPU_CLK_CFG
Address：0x40000090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD RTC
SEL
RTC
EN
RSVD RTC
DIV
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCDIV
Bits
Name Type Reset Description
31:20 RSVD
19 RTCSEL R/W 1 0: Bus clock 1: 32KHz
18 RTCEN R/W 0 CPU RTC clock enable
17 RSVD
16:0 RTCDIV R/W 17’h10 CPU RTC clock = (e21_rtc_sel) / (e21_rtc_div+1)
BL702/704/706 Reference Manual 49/ 375
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