BL702/704/706 Reference Manual
UART Clock
96M
Start
Stop
833
833
833
Baud rate˖115200 = 96M/833
Baud rate˖9600 = 96M/10000
10000
10000Sampling Time 5000
10000
Start
Fig. 10.3: UART sampling waveform
10.3.4 Transmitter
The transmitter contains a 128-byte transmit FIFO to store the data to be transmitted. Software can write TX FIFO
through APB bus, and can also move data into TX FIFO through DMA. When the transmit enable bit is set, the data
stored in the FIFO will be output from the TX pin. Software can choose to transfer data to TX FIFO through DMA or
APB bus. The software can check the status of the transmitter by querying the count value of the remaining available
space in the TX FIFO through the bit <TFICNT> of the register UART_FIFO_CONFIG_1. The FreeRun mode of the
transmitter is as follows: - If the FreeRun mode is not turned on, the sending behavior will be terminated and an
interrupt will be generated when the sent byte reaches the specified length. If you want to continue sending, you need
to turn off and then enable the send enable bit. - If the FreeRun mode is turned on, the transmitter will transmit when
there is data in the TX FIFO, and will not terminate because the transmitted byte reaches the specified length.
10.3.5 Receiver
The receiver contains a 128-byte receive FIFO to store the received data. The software can check the status of the
receiver by querying the count value of the available data in the RX FIFO through the bit <RFICNT> of the register
UART_FIFO_CONFIG_1. The lower 8 bits of the URX_RTO_TIMER register are used to set a receiving timeout
threshold. When the receiver does not receive data for more than this time value, it will trigger an interrupt. The
bits <DEGEN> and <DEGCNT> of the URX_CONFIG register are used to enable the deburring function and set the
threshold. It controls the filtering part before the UART sampling, and the UART will filter out the burrs whose width
is lower than the threshold in the waveform . Then send it to sampling.
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