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BL702/704/706 Reference Manual
TX FIFO underflow: When the size of the data filled in the TX FIFO does not meet the configured I2C data length
PKTLEN, and there is no new data to be filled into the TX FIFO, the register TFIU will be set;
TX FIFO overflow: After the two words of the TX FIFO are filled, before the data in the TX FIFO is sent out, fill the
TX FIFO with data again. The register TFIO will be set.
11.7 Using DMA
I2C can use DMA to send and receive data. Set DTEN to 1 to enable the DMA transmission mode. After a channel
is allocated for I2C, the DMA will transfer data from the memory area to the I2C_FIFO_WDATA register.
Set DREN to 1 to enable the DMA receive mode. After a channel is allocated for I2C, the DMA will transfer the data
in the I2C_FIFO_RDATA register to the memory area.
When the I2C module is used with DMA, the data part will be automatically carried by the DMA. There is no need for
the CPU to write data to the I2C TX FIFO or read data from the I2C RX FIFO.
11.7.1 DMA transmission process
1. Configure the read and write flag i2c_config[PKTDIR] to 0
2. Configure the slave device address i2c_config[SLVADDR]
3. Configure the slave device register address i2c_sub_addr, the slave device register address length i2c_config[SABC],
and configure the slave device register address enable bit i2c_config[SAEN] to 1
4. Set the length of the sent data i2c_config[PKTLEN]
5. Enable DMA mode transmission, set i2c_fifo_config_0[DTEN] to 1
6. Configure the data length of DMA transmission DMA_CxControl[TS] (x=0~7)
7. Configure DMA source address DMA_CxSrcAddr, data width DMA_CxControl[STW], burst size DMA_CxControl[SBS],
set DMA_CxControl[SI] to 1 to enable automatic address accumulation mode
8. Configure the DMA destination address DMA_CxDstAddr to i2c_fifo_wdata, data width DMA_CxControl[DTW] to
32 and burst size DMA_CxControl[DBS], clear DMA_CxControl[DI] to disable the address automatic accumulation
mode
9. Enable DMA
10. Configure i2c_config[MEN] to 1 to enable I2C
BL702/704/706 Reference Manual 213/ 375
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