Bouffalo Lab BL702 - Page 220

BL702/704/706 Reference Manual
11.9.8 i2c_fifo_config_0
Address：0x4000a380
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RFIU RFIO TFIU TFIO RFI
CLR
TFI
CLR
DREN DTEN
Bits
Name Type Reset Description
31:8 RSVD
7 RFIU R 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr
6 RFIO R 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr
5 TFIU R 1’b0 Underflow flag of TX FIFO, can be cleared by tx_fifo_clr
4 TFIO R 1’b0 Overflow flag of TX FIFO, can be cleared by tx_fifo_clr
3 RFICLR W1C 1’b0 Clear signal of RX FIFO
2 TFICLR W1C 1’b0 Clear signal of TX FIFO
1 DREN R/W 1’b0 Enable signal of dma_rx_req/ack interface
0 DTEN R/W 1’b0 Enable signal of dma_tx_req/ack interface
11.9.9 i2c_fifo_config_1
Address：0x4000a384
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD RFI
TH
RSVD TFI
TH
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RFICNT RSVD TFICNT
Bits
Name Type Reset Description
31:25 RSVD
24 RFITH R/W 1’d0 RX FIFO threshold, dma_rx_req will not be asserted if tx_-
fifo_cnt is less than this value
23:17 RSVD
16 TFITH R/W 1’d0 TX FIFO threshold, dma_tx_req will not be asserted if tx_-
fifo_cnt is less than this value
BL702/704/706 Reference Manual 220/ 375
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