BL702/704/706 Reference Manual
12.4.1 pwm_int_config
Address:0x4000a400
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD INTCLR RSVD INTSTS
Bits
Name Type Reset Description
31:14 RSVD
13:8 INTCLR W 6’d0 PWM channel interrupt clear
7:6 RSVD
5:0 INTSTS R 6’d0 PWM channel interrupt status
12.4.2 pwm0_clkdiv
Address:0x4000a420
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKDIV
Bits
Name Type Reset Description
31:16 RSVD
15:0 CLKDIV R/W 16’b0 PWM clock division
12.4.3 pwm0_thre1
Address:0x4000a424
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THRE1
BL702/704/706 Reference Manual 226/ 375
@2021 Bouffalo Lab