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BL702/704/706 Reference Manual

18.4.17 ep0_fifo_config

Address：0x4000d900

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD E0

RFU

RFO

TFU

TFO

RFC

TFC

DREN

DTEN

Bits

Name Type Reset Description

31:8 RSVD

7 E0RFU R 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr

6 E0RFO R 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr

5 E0TFU R 1’b0 Underflow flag of TX FIFO, can be cleared by tx_fifo_clr

4 E0TFO R 1’b0 Overflow flag of TX FIFO, can be cleared by tx_fifo_clr

3 E0RFC W1C 1’b0 Clear signal of RX FIFO

2 E0TFC W1C 1’b0 Clear signal of TX FIFO

1 E0DREN R/W 1’b0 Enable signal of dma_rx_req/ack interface

Set 1 when use DMA for rx FIFO data transfer

0 E0DTEN R/W 1’b0 Enable signal of dma_tx_req/ack interface

Set 1 when use DMA for tx FIFO data transfer

18.4.18 ep0_fifo_status

Address：0x4000d904

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RFF

RFE

RSVD E0RFC

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TFF

TFE

RSVD E0TFC

Bits

Name Type Reset Description

31 E0RFF R 1’b0 RX FIFO full flag

30 E0RFE R 1’b1 RX FIFO empty flag

29:23 RSVD

BL702/704/706 Reference Manual 333/ 375

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