BL702/704/706 Reference Manual
18.4.25 ep2_fifo_config
Address：0x4000d920
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD E2
RFU
E2
RFO
E2
TFU
E2
TFO
E2
RFC
E2
TFC
E2
DREN
E2
DTEN
Bits
Name Type Reset Description
31:8 RSVD
7 E2RFU R 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr
6 E2RFO R 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr
5 E2TFU R 1’b0 Underflow flag of TX FIFO, can be cleared by tx_fifo_clr
4 E2TFO R 1’b0 Overflow flag of TX FIFO, can be cleared by tx_fifo_clr
3 E2RFC W1C 1’b0 Clear signal of RX FIFO
2 E2TFC W1C 1’b0 Clear signal of TX FIFO
1 E2DREN R/W 1’b0 Enable signal of dma_rx_req/ack interface
Set 1 when use DMA for rx FIFO data transfer
0 E2DTEN R/W 1’b0 Enable signal of dma_tx_req/ack interface
Set 1 when use DMA for tx FIFO data transfer
18.4.26 ep2_fifo_status
Address：0x4000d924
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E2
RFF
E2
RFE
RSVD E2RFC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E2
TFF
E2
TFE
RSVD E2TFC
Bits
Name Type Reset Description
31 E2RFF R 1’b0 RX FIFO full flag
30 E2RFE R 1’b1 RX FIFO empty flag
29:23 RSVD
BL702/704/706 Reference Manual 337/ 375
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