BL702/704/706 Reference Manual
18.4.29 ep3_fifo_config
Address：0x4000d930
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD E3
RFU
E3
RFO
E3
TFU
E3
TFO
E3
RFC
E3
TFC
E3
DTEN
E3
DTEN
Bits
Name Type Reset Description
31:8 RSVD
7 E3RFU R 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr
6 E3RFO R 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr
5 E3TFU R 1’b0 Underflow flag of TX FIFO, can be cleared by tx_fifo_clr
4 E3TFO R 1’b0 Overflow flag of TX FIFO, can be cleared by tx_fifo_clr
3 E3RFC W1C 1’b0 Clear signal of RX FIFO
2 E3TFC W1C 1’b0 Clear signal of TX FIFO
1 E3DTEN R/W 1’b0 Enable signal of dma_rx_req/ack interface
Set 1 when use DMA for rx FIFO data transfer
0 E3DTEN R/W 1’b0 Enable signal of dma_tx_req/ack interface
Set 1 when use DMA for tx FIFO data transfer
18.4.30 ep3_fifo_status
Address：0x4000d934
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E3
RFF
E3
RFE
RSVD E3RFC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E3
TFF
E3
TFE
RSVD E3TFC
Bits
Name Type Reset Description
31 E3RFF R 1’b0 RX FIFO full flag
30 E3RFE R 1’b1 RX FIFO empty flag
29:23 RSVD
BL702/704/706 Reference Manual 339/ 375
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