BL702/704/706 Reference Manual
18.4.33 ep4_fifo_config
Address：0x4000d940
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD E4
RFU
E4
RFO
E4
TFU
E4
TFO
E4
RFC
E4
TFC
E4
DREN
E4
DTEN
Bits
Name Type Reset Description
31:8 RSVD
7 E4RFU R 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr
6 E4RFO R 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr
5 E4TFU R 1’b0 Underflow flag of TX FIFO, can be cleared by tx_fifo_clr
4 E4TFO R 1’b0 Overflow flag of TX FIFO, can be cleared by tx_fifo_clr
3 E4RFC W1C 1’b0 Clear signal of RX FIFO
2 E4TFC W1C 1’b0 Clear signal of TX FIFO
1 E4DREN R/W 1’b0 Enable signal of dma_rx_req/ack interface
Set 1 when use DMA for rx FIFO data transfer
0 E4DTEN R/W 1’b0 Enable signal of dma_tx_req/ack interface
Set 1 when use DMA for tx FIFO data transfer
18.4.34 ep4_fifo_status
Address：0x4000d944
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E4
RFF
E4
RFE
RSVD E4RFC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E4
TFF
E4
TFE
RSVD E4TFC
Bits
Name Type Reset Description
31 E4RFF R 1’b0 RX FIFO full flag
30 E4RFE R 1’b1 RX FIFO empty flag
29:23 RSVD
BL702/704/706 Reference Manual 341/ 375
@2021 Bouffalo Lab
To Next Page