BL702/704/706 Reference Manual
18.4.37 ep5_fifo_config
Address：0x4000d950
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD E5
RFU
E5
RFO
E5
TFU
E5
TFO
E5
RFC
E5
TFC
E5
DREN
E5
DTEN
Bits
Name Type Reset Description
31:8 RSVD
7 E5RFU R 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr
6 E5RFO R 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr
5 E5TFU R 1’b0 Underflow flag of TX FIFO, can be cleared by tx_fifo_clr
4 E5TFO R 1’b0 Overflow flag of TX FIFO, can be cleared by tx_fifo_clr
3 E5RFC W1C 1’b0 Clear signal of RX FIFO
2 E5TFC W1C 1’b0 Clear signal of TX FIFO
1 E5DREN R/W 1’b0 Enable signal of dma_rx_req/ack interface
Set 1 when use DMA for rx FIFO data transfer
0 E5DTEN R/W 1’b0 Enable signal of dma_tx_req/ack interface
Set 1 when use DMA for tx FIFO data transfer
18.4.38 ep5_fifo_status
Address：0x4000d954
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E5
RFF
E5
RFE
RSVD E5RFC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E5
TFF
E5
TFE
RSVD E5TFC
Bits
Name Type Reset Description
31 E5RFF R 1’b0 RX FIFO full flag
30 E5RFE R 1’b1 RX FIFO empty flag
29:23 RSVD
BL702/704/706 Reference Manual 343/ 375
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