BL702/704/706 Reference Manual
Inside the ADC module, a clock divider is provided, which can divide the input clock by 1/4/8/12/16/20/24/32. Users
can adjust the ADC clock source and various frequency division coefficients according to actual sampling require-
ments. Note that the maximum input clock of ADC is 2MHZ.
The width of the gpadc_32m_clk_div divider register is 6bits, the maximum divider is 64, and the divider formula is
fout=fsource/(gpadc_32m_clk_div+1).
The gpadc_clk_div_ratio divider register is located inside the ADC module, with a width of 3bits, and its divider value
is defined as follows:
ADC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */
ADC_CLK_DIV_4, /*!< ADC clock:on 32M clock is 8M */
ADC_CLK_DIV_8, /*!< ADC clock:on 32M clock is 4M */
ADC_CLK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */
ADC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */
ADC_CLK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */
ADC_CLK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */
ADC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */
If the user wants to adjust the ADC input clock, there are four ways.
1. Switch the clock source, XTAL defaults to 32MHZ, Audio PLL (can be configured to 11.288MHZ or 11.2896MHZ).
2. Use a frequency divider with a length of 6BITS in the clock module.
3. Using the frequency divider in the ADC module, the optional frequency division is 1/4/8/12/16/20/24/32.
4. By configuring the gpadc_res_sel register, change the value of OSR to achieve the frequency effect. If OSR=256,
the actual equivalent ADC input clock is divided by 256.
Assuming that the clock source selection is Audio PLL=11.2896MHZ, the GLB frequency division selection configu-
ration is 1, the ADC internal frequency divider is selected ADC_CLK_DIV_4, OSR=128, then the final clock output is
fout = 11289600 / (1 + 1) / 4/128 = 11025HZ
4.3.4 ADC conversion mode
The ADC supports two conversion modes: single-channel conversion mode and scan mode.
In single-channel conversion mode, the user needs to select the positive input channel through gpadc_pos_sel, select
the negative input channel through gpadc_neg_sel, and set the gpadc_cont_conv_en control bit to 0, which means
single-channel conversion, and then set the gpadc_conv_start control bit to start the conversion.
In scan conversion mode, the gpadc_cont_conv_en control bit needs to be set to 1, and the number of conversion
channels set by the ADC according to the gpadc_scan_length control bit. According to the channel order set by the
gpadc_reg_scn_posX (X = 1, 2) and gpadc_reg_scn_negX (X = 1, 2) registers, the conversion is performed one by
one, and the result of the conversion is automatically pushed into the ADC FIFO. The channels set by the gpadc_-
reg_scn_posX (X = 1, 2) and gpadc_reg_scn_negX (X = 1, 2) registers can be the same, which means that users can
BL702/704/706 Reference Manual 94/ 375
@2021 Bouffalo Lab
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