Vectored Interrupt Controller (VIC) 108 May 03, 2004
Philips Semiconductors Preliminary User Manual
LPC2119/2129/2194/2292/2294ARM-based Microcontroller
Solution 2: Disable IRQs and FIQs using separate writes to the CPSR, eg:
MRS r0, cpsr
ORR r0, r0, #I_Bit ;disable IRQs
MSR cpsr_c, r0
ORR r0, r0, #F_Bit ;disable FIQs
MSR cpsr_c, r0
This is the best workaround where the maximum time for which FIQs are disabled is critical (it does not increase this time at all).
However, it does not solve problem one, and requires extra instructions at every point where IRQs and FIQs are disabled
together.
Solution 3: Re-enable FIQs at the beginning of the IRQ handler. As the required state of all bits in the c field of the CPSR are
known, this can be most efficiently be achieved by writing an immediate value to CPSR_c, for example:
MSR cpsr_c, #I_Bit:OR:irq_MODE ;IRQ should be disabled
;FIQ enabled
;ARM state, IRQ mode
This requires only the IRQ handler to be modified, and FIQs may be re-enabled more quickly than by using workaround 1.
However, this should only be used if the system can guarantee that FIQs are never disabled while IRQs are enabled. It does not
address problem one.
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