Philips LPC2129 - Architecture; Figure 32: I2 C Architecture

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I2C Interface 177 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2119/2129/2194/2292/2294ARM-based Microcontroller

ARCHITECTURE

Figure 32: I

C Architecture

Address Register

Comparator

Shift Register

ACK

Bit Counter /

Arbitration &

Sync Logic

Serial Clock

Generator

Timing &

Control

Logic

Control Register & SCL Duty

Cycle Registers

Status

Decoder

Status Register

Input

Filter

Output

Stage

VPB BUS

SDA

I2CONSET

I2CONCLR

I2SCLH

I2SCLL

Status Bus

I2STAT

pclk

Interrupt

I2DAT

I2ADR

SCL

Input

Filter

Output

Stage

Main Page

Table of Contents3
List of Figures7
List of Tables9
Document Revision History14
Introduction16
General Description16
Features16
Applications17
Device Information17
Table 1: LPC2119/2129/2194/2292/2294 Device Information17
Architectural Overview18
ARM7TDMI-S Processor18
On-Chip Flash Memory System18
On-Chip Static RAM19
Block Diagram20
Figure 1: LPC2119/2129/2194/2292/2294 Block Diagram20
LPC2119/2129/2292/2194/2294 Registers21
Table 2: LPC2119/2129/2194/2292/2294 Registers22
LPC2119/2129/2292/2294 Memory Addressing48
Memory Maps48
Figure 2: System Memory Map48
Figure 3: Peripheral Memory Map49
Figure 4: AHB Peripheral Map50
Figure 5: VPB Peripheral Map51
LPC2119/2129/2194/2292/2294 Memory Re-Mapping and Boot Block52
Table 3: ARM Exception Vector Locations52
Table 4: LPC2119/2129/2194/2292/2294 Memory Mapping Modes52
Figure 6: Map of Lower Memory Is Showing Re-Mapped and Re-Mappable Areas (128 Kb Flash)54
Prefetch Abort and Data Abort Exceptions55
External Memory Controller (EMC)56
Features56
Description56
Table 5: Address Ranges of External Memory Banks (Lpc2292/2294Only)56
Pin Description57
Register Description57
Table 6: External Memory Controller Pin Description57
Table 7: External Memory Controller Register Map57
Table 8: Bank Configuration Registers 0-3 (BCFG0-3 - 0Xffe00000-0C)58
Table 9: Default Memory Widths at Reset58
External Memory Interface59
Figure 7: 32 Bit Bank External Memory Interfaces59
Figure 8: 16 Bit Bank External Memory Interfaces60
Figure 9: 8 Bit Bank External Memory Interface60
Typical Bus Sequences61
Figure 10: External Memory Read Access (WST1=0 and WST1=1 Examples)61
Figure 11: External Memory Write Access (WST2=0 and WST2=1 Examples)61
External Memory Selection62
Table 10: External Memory and System Requirements62
System Control Block64
Summary of System Control Block Functions64
Pin Description64
Table 11: Pin Summary64
Register Description66
Table 12: Summary of System Control Registers66
Crystal Oscillator67
Figure 12: Oscillator Modes and Models: A) Slave Mode of Operation, B) Oscillation Mode of Operation67
Table 13: Recommended Values for CX1/X2 in Oscillation Mode (Crystal and External Components Parameters)67
Figure 13: FOSC Selection Algorithm68
External Interrupt Inputs69
Table 14: External Interrupt Registers69
Table 15: External Interrupt Flag Register (EXTINT - 0Xe01Fc140)70
Table 16: External Interrupt Wakeup Register (EXTWAKE - 0Xe01Fc144)71
Table 17: External Interrupt Mode Register (EXTMODE - 0Xe01Fc148)71
Table 18: External Interrupt Polarity Register (EXTPOLAR - 0Xe01Fc14C)72
Figure 14: External Interrupt Logic73
Memory Mapping Control74
Table 19: MEMMAP Register74
Table 20: Memory Mapping Control Register (MEMMAP - 0Xe01Fc040)74
PLL (Phase Locked Loop)75
Table 21: PLL Registers75
Figure 15: PLL Block Diagram76
Table 22: PLL Control Register (PLLCON - 0Xe01Fc080)77
Table 23: PLL Configuration Register (PLLCFG - 0Xe01Fc084)77
Table 24: PLL Status Register (PLLSTAT - 0Xe01Fc088)78
Table 25: PLL Control Bit Combinations78
Table 26: PLL Feed Register (PLLFEED - 0Xe01Fc08C)79
Table 27: PLL Divider Values80
Table 28: PLL Multiplier Values80
Power Control81
Table 29: Power Control Registers81
Table 30: Power Control Register (PCON - 0Xe01Fc0C0)82
Table 31: Power Control for Peripherals Register for LPC2119/2129/2292 (PCONP - 0Xe01Fc0C4)82
Table 32: Power Control for Peripherals Register for LPC2194/2294 (PCONP - 0Xe01Fc0C4)83
Power Control Usage Notes84
Reset85
Figure 16: Reset Block Diagram Including Wakeup Timer85
VPB Divider86
Table 33: VPBDIV Register Map86
Table 34: VPB Divider Register (VPBDIV - 0Xe01Fc100)86
Figure 17: VPB Divider Connections87
Wakeup Timer88
Memory Accelerator Module (MAM)90
Introduction90
Figure 18: Simplified Block Diagram of the Memory Accelerator Module91
Memory Accelerator Module Operating Modes92
Table 35: MAM Responses to Program Accesses of Various Types92
Table 36: MAM Responses to Data and DMA Accesses of Various Types92
MAM Configuration93
Register Description93
Table 37: Summary of System Control Registers93
MAM Usage Notes94
Table 38: MAM Control Register (MAMCR - 0Xe01Fc000)94
Table 39: MAM Timing Register (MAMTIM - 0Xe01Fc004)94
Vectored Interrupt Controller (VIC)96
Features96
Description96
Register Description97
Table 40: VIC Register Map97
VIC Registers99
Table 41: Software Interrupt Register (Vicsoftint - 0Xfffff018, Read/Write)99
Table 42: Software Interrupt Clear Register (Vicsoftintclear - 0Xfffff01C, Write Only)99
Table 43: Raw Interrupt Status Register (Vicrawintr - 0Xfffff008, Read-Only)99
Table 44: Interrupt Enable Register (Vicintenable - 0Xfffff010, Read/Write)100
Table 45: Software Interrupt Clear Register (Vicintenclear - 0Xfffff014, Write Only)100
Table 46: Interrupt Select Register (Vicintselect - 0Xfffff00C, Read/Write)100
Table 47: IRQ Status Register (Vicirqstatus - 0Xfffff000, Read-Only)100
Table 48: IRQ Status Register (Vicfiqstatus - 0Xfffff004, Read-Only)101
Table 49: Vector Control Registers (Vicvectcntl0-15 - 0Xfffff200-23C, Read/Write)101
Table 50: Vector Address Registers (Vicvectaddr0-15 - 0Xfffff100-13C, Read/Write)101
Table 51: Default Vector Address Register (Vicdefvectaddr - 0Xfffff034, Read/Write)101
Table 52: Vector Address Register (Vicvectaddr - 0Xfffff030, Read/Write)102
Table 53: Protection Enable Register (Vicprotection - 0Xfffff020, Read/Write)102
Interrupt Sources103
Table 54: Connection of Interrupt Sources to the Vectored Interrupt Controller103
Figure 19: Block Diagram of the Vectored Interrupt Controller105
Spurious Interrupts106
VIC Usage Notes109
Pin Configuration110
LPC2119/2129/2194 Pinout110
Figure 20: LPC2119/2129/2194 64-Pin Package110
Pin Description for LPC2119/2129/2194111
Table 55: Pin Description for LPC2119/2129/2194111
LPC2292/2294 Pinout116
Figure 21: LPC2292/2294 144-Pin Package116
Pin Description for LPC2292/2294117
Table 56: Pin Description for LPC2292/2294117
Pin Connect Block126
Features126
Applications126
Description126
Register Description126
Table 57: Pin Connect Block Register Map126
Table 58: Pin Function Select Register 0 for LPC2119/2129/2292 (PINSEL0 - 0Xe002C000)127
Table 59: Pin Function Select Register 0 for LPC2194/2294 (PINSEL0 - 0Xe002C000)127
Table 60: Pin Function Select Register 1 for LPC2119/2129/2292 (PINSEL1 - 0Xe002C004)128
Table 61: Pin Function Select Register 1 for LPC2194/2294 (PINSEL1 - 0Xe002C004)129
Table 62: Pin Function Select Register 2 for LPC2119/2129/2194 (PINSEL2 - 0Xe002C014)129
Table 63: Pin Function Select Register 2 for LPC2292/2294 (PINSEL2 - 0Xe002C014)131
Table 64: Pin Function Select Register Bits132
Boot Control on 144-Pin Package133
Table 65: Boot Control on BOOT1:0133
Gpio134
Features134
Applications134
Pin Description134
Register Description134
Table 66: GPIO Pin Description134
Table 67: GPIO Register Map135
Table 68: GPIO Pin Value Register (IO0PIN - 0Xe0028000, IO1PIN - 0Xe0028010, IO2PIN - 0Xe0028020, IO3PIN - 0Xe0028030)136
Table 69: GPIO Output Set Register (IO0SET - 0Xe0028004, IO1SET - 0Xe0028014, IO2SET - 0Xe0028024, IO3SET - 0Xe0028034)136
GPIO Usage Notes137
Table 70: GPIO Output Clear Register (IO0CLR - 0Xe002800C, IO1CLR - 0Xe002801C, IO2CLR - 0Xe002802C, IO3CLR - 0Xe002803C)137
Table 71: GPIO Direction Register (IO0DIR - 0Xe0028008, IO1DIR - 0Xe0028018, IO2DIR - 0Xe0028028, IO3DIR - 0Xe0028038)137
10. Uart0140
Features140
Pin Description140
Table 72: UART0 Pin Description140
Register Description141
Table 73: UART0 Register Map141
Table 74: UART0 Receiver Buffer Register (U0RBR - 0Xe000C000 When DLAB = 0, Read Only)142
Table 75: UART0 Transmit Holding Register (U0THR - 0Xe000C000 When DLAB = 0, Write Only)142
Table 76: UART0 Divisor Latch LSB Register (U0DLL - 0Xe000C000 When DLAB = 1)142
Table 77: UART0 Divisor Latch MSB Register (U0DLM - 0Xe000C004 When DLAB = 1)142
Table 78: UART0 Interrupt Enable Register Bit Descriptions (U0IER - 0Xe000C004 When DLAB = 0)143
Table 79: UART0 Interrupt Identification Register Bit Descriptions (U0IIR - 0Xe000C008, Read Only)143
Table 80: UART0 Interrupt Handling144
Table 81: UART0 FIFO Control Register Bit Descriptions (U0FCR - 0Xe000C008)145
Table 82: UART0 Line Control Register Bit Descriptions (U0LCR - 0Xe000C00C)146
Table 83: UART0 Line Status Register Bit Descriptions (U0LSR - 0Xe000C014, Read Only)147
Table 84: UART0 Scratchpad Register (U0SCR - 0Xe000C01C)148
Architecture149
Figure 22: UART0 Block Diagram150
11. Uart1152
Features152
Pin Description152
Table 85: UART1 Pin Description152
Register Description153
Table 86: UART1 Register Map153
Table 87: UART1 Receiver Buffer Register (U1RBR - 0Xe0010000 When DLAB = 0, Read Only)154
Table 88: UART1 Transmit Holding Register (U1THR - 0Xe0010000 When DLAB = 0, Write Only)154
Table 89: UART1 Divisor Latch LSB Register (U1DLL - 0Xe0010000 When DLAB = 1)154
Table 90: UART1 Divisor Latch MSB Register (U1DLM - 0Xe0010004 When DLAB = 1)155
Table 91: UART1 Interrupt Enable Register Bit Descriptions (U1IER - 0Xe0010004 When DLAB = 0)155
Table 92: UART1 Interrupt Identification Register Bit Descriptions (IIR - 0Xe0010008, Read Only)156
Table 93: UART1 Interrupt Handling157
Table 94: UART1 FCR Bit Descriptions (U1FCR - 0Xe0010008)158
Table 95: UART1 Line Control Register Bit Descriptions (U1LCR - 0Xe001000C)159
Table 96: UART1 Modem Control Register Bit Descriptions (U1MCR - 0Xe0010010)160
Table 97: UART1 Line Status Register Bit Descriptions (U1LSR - 0Xe0010014, Read Only)161
Table 98: UART1 Modem Status Register Bit Descriptions (U1MSR - 0X0Xe0010018)162
Table 99: UART1 Scratchpad Register (U1SCR - 0Xe001001C)163
Architecture164
Figure 23: UART1 Block Diagram165
I2C Interface166
Features166
Applications166
Description166
Figure 24: I2C Bus Configuration167
Figure 25: Slave Mode Configuration167
Figure 26: Format in the Master Transmitter Mode168
Figure 27: Format of Master Receiver Mode168
Figure 28: a Master Receiver Switch to Master Transmitter after Sending Repeated START169
Figure 29: Slave Mode Configuration169
Pin Description170
Figure 30: Format of Slave Receiver Mode170
Figure 31: Format of Slave Transmitter Mode170
Table 100: I2C Pin Description170
Register Description171
Table 101: I2C Register Map171
Table 102: I2C Control Set Register (I2CONSET - 0Xe001C000)173
Table 103: I2C Control Clear Register (I2CONCLR - 0Xe001C018)173
Table 104: I2C Status Register (I2STAT - 0Xe001C004)174
Table 105: I2C Data Register (I2DAT - 0Xe001C008)174
Table 106: I2C Slave Address Register (I2ADR - 0Xe001C00C)174
Table 107: I2C SCL High Duty Cycle Register (I2SCLH - 0Xe001C010)175
Table 108: I2C SCL Low Duty Cycle Register (I2SCLL - 0Xe001C014)175
Table 109: I2C Clock Rate Selections for VPB Clock Divider = 1175
Table 110: I2C Clock Rate Selections for VPB Clock Divider = 2176
Table 111: I2C Clock Rate Selections for VPB Clock Divider = 4176
Architecture177
Figure 32: I2C Architecture177
SPI Interface178
Features178
Description178
Figure 33: SPI Data Transfer Format (CPHA = 0 and CPHA = 1)179
Table 112: SPI Data to Clock Phase Relationship179
Pin Description182
Table 113: SPI Pin Description182
Register Description183
Table 114: SPI Register Map183
Table 115: SPI Control Register (S0SPCR - 0Xe0020000, S1SPCR - 0Xe0030000)183
Table 116: SPI Status Register (S0SPSR - 0Xe0020004, S1SPSR - 0Xe0030004)184
Table 117: SPI Data Register (S0SPDR - 0Xe0020008, S1SPDR - 0Xe0030008)184
Table 118: SPI Clock Counter Register (S0SPCCR - 0Xe002000C, S1SPCCR - 0Xe003000C)184
Table 119: SPI Interrupt Register (S0SPINT - 0Xe002001C, S1SPINT - 0Xe003001C)185
Architecture186
Figure 34: SPI Block Diagram186
14. Can Controllers and Acceptance Filter188
CAN Controllers188
Features188
Pin Description189
Memory Map of the CAN Block189
CAN Controller Registers189
Table 120: CAN Pin Descriptions189
Table 121: Memory Map of the CAN Block189
Table 122: CAN Acceptance Filter and Central CAN Registers189
Table 123: CAN1, CAN2, CAN3 and CAN4 Controller Register Map190
Table 124: CAN Mode Register (CANMOD - 0Xe00X X000)192
Table 125: CAN Command Register (CANCMR - 0Xe00X X004)193
Table 126: CAN Global Status Register (CANGSR - 0Xe00X X008)194
Table 127: CAN Interrupt and Capture Register (CANICR - 0Xe00X X00C)195
Table 128: CAN Interrupt Enable Register (CANIER - 0Xe00X X010)196
Table 129: CAN Bus Timing Register (CANBTR - 0Xe00X X014)197
Table 130: CAN Error Warning Limit Register (CANEWL - 0Xe00X X018)197
Table 131: CAN Status Register (CANSR - 0Xe00X X01C)197
Table 132: CAN Rx Frame Status Register (CANRFS - 0Xe00X X020)199
Table 133: CAN Rx Identifier Register When FF=0 (CANRID - 0Xe00X X024)199
Table 134: CAN Rx Identifier Register When FF=1 (CANRID - 0Xe00X X024)199
Table 135: CAN Rx Data Register 1 (CANRDA - 0Xe00X X028)200
Table 136: CAN Rx Data Register B (CANRDB - 0Xe00X X02C)200
Table 137: CAN Tx Frame Information Register (CANTFI1, 2, 3 - 0Xe00X X030, 40, 50)201
Table 138: CAN Tx Identifier Register When FF=0 (CANTID1, 2, 3 - 0Xe00X X034, 44, 54)201
Table 139: CAN Tx Identifier Register When FF=1 (CANTID1, 2, 3 - 0Xe00X X034, 44, 54)201
CAN Controller Operation202
Table 140: CAN Tx Data Register a (CANTDA1, 2, 3 - 0Xe00X X038, 48, 58)202
Table 141: CAN Tx Data Register B (CANTDB1, 2, 3 - 0Xe00X X03C, 4C, 5C)202
Centralized CAN Registers204
Table 142: CAN Central Transmit Status Register (Cantxsr - 0Xe004 0000)204
Table 143: CAN Central Receive Status Register (Canrxsr - 0Xe004 0004)204
Global Acceptance Filter205
Figure 35: Entry in Fullcan and Individual Standard Identifier Tables205
Figure 36: Entry in Standard Identifier Range Table205
Table 144: CAN Central Miscellaneous Status Register (CANMSR - 0Xe004 0008)205
Figure 37: Entry in Either Extended Identifier Table206
Acceptance Filter Registers207
Table 145: Acceptance Filter Modes Register (AFMR - 0Xe003 C000)207
Table 146: Standard Frame Start Address Register (Sff_Sa - 0Xe003 C004)207
Table 147: Standard Frame Group Start Address Reg (Sff_Grp_Sa - 0Xe003 C008)207
Table 148: Extended Frame Start Address Register (Eff_Sa - 0Xe003 C00C)208
Table 149: Extended Frame Group Start Addr Register (Eff_Grp_Sa - 0Xe003 C010)208
Table 150: End of AF Tables Register (Endoftable - 0Xe003 C014)208
Table 151: LUT Error Address Register (Luterrad - 0Xe003 C018)208
Examples of Acceptance Filter Tables and ID Index Values209
Table 152: LUT Error Register (Luterr - 0Xe003 C01C)209
Table 153: Example of Acceptance Filter Tables and ID Index Values209
Fullcan Mode210
Figure 38: Detailed Example of Acceptance Filter Tables and ID Index Values210
Table 154: Format of Automatically Stored Rx Message211
15. Timer0 and Timer1214
Features214
Applications214
Description215
Pin Description215
Table 155: Pin Summary215
Register Description216
Table 156: TIMER0 and TIMER1 Register Map216
Table 159: Match Control Register (MCR: TIMER0 - T0MCR: 0Xe0004014; TIMER1 - T1MCR: 0Xe0008014)218
Table 160: Capture Control Register (CCR: TIMER0 - T0CCR: 0Xe0004028; TIMER1 - T1CCR: 0Xe0008028)219
Example Timer Operation221
Figure 39: a Timer Cycle in Which PR=2, Mrx=6, and both Interrupt and Reset on Match Are Enabled221
Figure 40: a Timer Cycle in Which PR=2, Mrx=6, and both Interrupt and Stop on Match Are Enabled221
Architecture222
Figure 41: Timer Block Diagram222
Table 157: Interrupt Register222
Table 158: Timer Control Register222
Pulse Width Modulator (PWM)224
Features224
Description224
Figure 42: PWM Block Diagram226
Figure 43: Sample PWM Waveforms227
Pin Description229
Register Description230
17. A/D Converter238
Features238
Description238
Pin Descriptions238
Register Description238
Operation240
18. Real Time Clock242
Features242
Description242
Architecture243
Register Description243
Figure 44: RTC Block Diagram243
RTC Interrupts245
Miscellaneous Register Group246
Consolidated Time Registers249
Time Counter Group251
Alarm Register Group252
RTC Usage Notes252
Reference Clock Divider (Prescaler)253
Figure 45: RTC Prescaler Block Diagram254
19. Watchdog256
Features256
Applications256
Description256
Register Description257
Usage Notes on Watchdog Reset and External Start259
Block Diagram261
Figure 46: Watchdog Block Diagram261
20. Flash Memory System and Programming262
Flash Memory System262
Flash Boot Loader262
Features262
Applications262
Description262
Figure 47: Map of Lower Memory after any Reset (128 Kb Flash Part)263
Boot Process Flowchart266
Figure 48: Boot Process Flowchart (Bootloader Revisions before 1.61)266
Figure 49: Boot Process Flowchart (Bootloader Revisions 1.61 and Later)267
Sector Numbers268
Code Read Protection269
Figure 50: IAP Parameter Passing281
Table 217: IAP Blank Check Sector(S) Command Description283
Table 218: IAP Read Part ID Command Description283
Table 219: IAP Read Boot Code Version Command Description283
Table 220: IAP Compare Command Description284
Table 221: IAP Status Codes Summary284
JTAG FLASH Programming Interface285
Embeddedice Logic286
Features286
Applications286
Description286
Pin Description287
Reset State of Multiplexed Pins287
Table 222: Embeddedice Pin Description287
Register Description288
Table 223: Embeddedice Logic Registers288
Block Diagram289
Figure 51: Embeddedice Debug Environment Block Diagram289
22. Embedded Trace Macrocell290
Features290
Applications290
Description290
Table 224: ETM Configuration290
Pin Description291
Reset State of Multiplexed Pins291
Table 225: ETM Pin Description291
Register Description292
Table 226: ETM Registers292
Block Diagram293
Figure 52: ETM Debug Environment Block Diagram293
23. Realmonitor294
Features294
Applications294
Description294
Figure 53: Realmonitor Components295
Figure 54: Realmonitor as a State Machine296
How to Enable Realmonitor298
Table 227: Realmonitor Stack Requirement298
Realmonitor Build Options304

Philips LPC2129 - Architecture; Figure 32: I2 C Architecture

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