System Control Block 64 May 03, 2004
Philips Semiconductors Preliminary User Manual
LPC2119/2129/2194/2292/2294ARM-based Microcontroller
4. SYSTEM CONTROL BLOCK
SUMMARY OF SYSTEM CONTROL BLOCK FUNCTIONS
The System Control Block includes several system features and control registers for a number of functions that are not related
to specific peripheral devices. These include:
• Crystal Oscillator.
• External Interrupt Inputs.
• Memory Mapping Control.
• PLL.
• Power Control.
• Reset.
• VPB Divider.
• Wakeup Timer.
Each type of function has its own register(s) if any are required and unneeded bits are defined as reserved in order to allow future
expansion. Unrelated functions never share the same register addresses.
PIN DESCRIPTION
Table 11 shows pins that are associated with System Control block functions.
Table 11: Pin summary
Pin name Pin direction Pin Description
X1 Input Crystal Oscillator Input- Input to the oscillator and internal clock generator circuits.
X2 Output Crystal Oscillator Output- Output from the oscillator amplifier.
EINT0 Input
External Interrupt Input 0- An active low general purpose interrupt input. This pin may be
used to wake up the processor from Idle or Power down modes.
Pins P0.1 and P0.16 can be selected to perform EINT0 function.
LOW level on this pin immediately after reset is considered as an external hardware
request to start the ISP command handler. More details on ISP and Flash memory can be
found in "Flash Memory System and Programming" chapter.
EINT1 Input
External Interrupt Input 1- See the EINT0 description above.
Pins P0.3 and P0.14 can be selected to perform EINT1 function.
EINT2 Input
External Interrupt Input 2- See the EINT0 description above.
Pins P0.7 and P0.15 can be selected to perform EINT2 function.
EINT3 Input
External Interrupt Input 3- See the EINT0 description above.
Pins P0.9, P0.20 and P0.30 can be selected to perform EINT3 function.
R
ESET Input
External Reset input- A low on this pin resets the chip, causing I/O ports and peripherals
to take on their default states, and the processor to begin execution at address 0.
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