14 May 03, 2004
Philips Semiconductors Preliminary User Manual
LPC2119/2129/2194/2292/2294ARM-based Microcontroller
DOCUMENT REVISION HISTORY
2003 Dec 03:
• Prototype LPC2119/2129/2194/2292/2294 User Manual created from the design specification.
2003 Dec 09:
• External Memory Controller and Pin Connect Block chapters updated.
2003 Dec 15/16:
• System Control Block chapter updated.
2003 Dec 18:
• A/D Converter Block chapter updated.
2004 Jan 07:
• CAN and PLL related material updated.
2004 Jan 26:
• System Control Block (Crystal Oscillator section - new frequencies added) and CAN Chapter updated.
2004 Feb 03:
• Introduction chapter (register list) updated.
2004 May 03:
• P0.16 description in "Pin Connect Block" chapter corrected from "Reserved" to "Capture 0.2 (TIMER0)".
• LPC2212 Flash size corrected in "Introduction" chapter corrected from 256 to 128 kB.
• Interrupt source #17 in "Vectored Interrupt Controller (VIC)" corrected from "EINT2" to "EINT3".
• Parallel ports 2 and 3 related registers added to "Introduction" and "GPIO" chapters
• Trigger levels determined by bits 7 and 6 in U0FCR and U1FCR ("UART0" and "UART1" chapters) now showed in both decimal
and hexadecimal notations
• References to DBGSEL pin removed from entire document (pin does not exist in this family of microcontrollers)
• Pin 20 in figure showing 64-pin package ("Pin Configuration" chapter) corrected from "1.3" to "1.31"
•V
ddA
replaced with V
3A
in "A/D Converter" chapter and V
3A
description updated in "Pin Configuration" chapter
• Warning on analog input levels added to "A/D Converter" chapter
• On-chip upper RAM boundary corrected from 0x4000 1FFF to 0x4000 3FFF in "LPC2119/2129/2292/2294 Memory
Addressing" chapter
• Port pin tolerance, pull-up presence and voltage considerations added in "Pin Configuration" and "A/D Converter" chapter
• Baudrates in "Flash Memory System and Programming" corrected: 115200 and 230400 instead of 115000 and 230000
• CAN related interrupt sources fixed in "Vectored Interrupt Controller (VIC)" chapter
• ERRBIT field in CANICR CAN register ("Vectored Interrupt Controller (VIC)" chapter) updated
• Number of the on-chip Flash erase and write cycles added into "Introduction" and "Flash Memory System and Programming"
chapters
• Pins capable of providing an External Interrupt functionality are acounted and listed in "System Control Block" chapter
• Access to ports with respect to GPIO configured pins clarified in "GPIO" and "Pin Connect Block" chapters
• Description of Code Read Protection feature added in "Flash Memory System and Programming" chapter
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