SPI Interface 178 May 03, 2004
Philips Semiconductors Preliminary User Manual
LPC2119/2129/2194/2292/2294ARM-based Microcontroller
13. SPI INTERFACE
FEATURES
• Two complete and independent SPI cintrollers
• Compliant with Serial Peripheral Interface (SPI) specification.
• Synchronous, Serial, Full Duplex Communication.
• Combined SPI master and slave.
• Maximum data bit rate of one eighth of the input clock rate.
DESCRIPTION
SPI Overview
SPI0 and SPI1 are full duplex serial interfaces. They can handle multiple masters and slaves being connected to a given bus.
Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer
the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master.
SPI Data Transfers
Figure 33 is a timing diagram that illustrates the four different data transfer formats that are available with the SPI. This timing
diagram illustrates a single 8 bit data transfer. The first thing one should notice in this timing diagram is that it is divided into three
horizontal parts. The first part describes the SCK and SSEL signals. The second part describes the MOSI and MISO signals when
the CPHA variable is 0. The third part describes the MOSI and MISO signals when the CPHA variable is 1.
In the first part of the timing diagram, note two points. First, the SPI is illustrated wit CPOL set to both 0 and 1. The second point
to note is the activation and de-activation of the SSEL signal. When CPHA = 1, the SSEL signal will always go inactive between
data transfers. This is not guaranteed when CPHA = 0 (the signal can remain active).
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