I2C Interface 175 May 03, 2004
Philips Semiconductors Preliminary User Manual
LPC2119/2129/2194/2292/2294ARM-based Microcontroller
I
2
C SCL Duty Cycle Registers (I2SCLH - 0xE001C010 and I2SCLL - 0xE001C014)
Software must set values for registers I2SCLH and I2SCLL to select the appropriate data rate. I2SCLH defines the number of
pclk cycles for SCL high, I2SCLL defines the number of pclk cycles for SCL low. The frequency is determined by the following
formula:
Bit Frequency = f
CLK
/ (I2SCLH + I2SCLL)
Where f
CLK
is the frequency of pclk.
The values for I2SCLL and I2SCLH don’t have to be the same. Software can set different duty cycles on SCL by setting these
two registers. But the value of the register must ensure that the data rate is in the I
2
C data rate range of 0 through 400KHz. So
the value of I2SCLL and I2SCLH has some restrictions. Each register value should be greater than or equal to 4.
Table 108: I
2
C SCL High Duty Cycle Register (I2SCLH - 0xE001C010)
I2SCLH Function Description
Reset
Value
15:0 Count Count for SCL HIGH time period selection 0x 0004
Table 109: I
2
C SCL Low Duty Cycle Register (I2SCLL - 0xE001C014)
I2SCLL Function Description
Reset
Value
15:0 Count Count for SCL LOW time period selection 0x 0004
Table 110: I2C Clock Rate Selections for VPB Clock Divider = 1
I2SCLL+
I2SCLH
Bit Frequency (kHz) At f
CCLK
(MHz) & VPB Clock Divider = 1
16 20 40 60
8- - - -
10----
25----
50 320.0 400.0 - -
75 213.333 266.667 - -
100 160.0 200.0 400.0 -
160 100.0 125.0 250.0 375.0
200 80.0 100.0 200.0 300.0
320 50.0 62.5 125.0 187.5
400 40.0 50.0 100.0 150.0
510 31.373 39.216 78.431 117.647
800 20.0 25.0 50.0 75.0
1280 12.5 15.625 31.25 46.875
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