A/D Converter 239 May 03, 2004
Philips Semiconductors Preliminary User Manual
ARM-based Microcontroller
LPC2119/2129/2194/2292/2294
A/D Control Register (ADCR - 0xE0034000)
Table 174: A/D Control Register (ADCR - 0xE0034000)
ADCR Name Description Reset Value
7:0 SEL
Selects which of the Ain3:0 (LPC2119/2129/2194) or Ain7:0 (LPC2292/2294) pins is (are) to
be sampled and converted. Only bits 3:0 should be set to 1 in the 48 or 64 pin package. In
software-controlled mode, only one of these bits should be 1. In hardware scan mode, any
value containing 1 to 8 ones (1 to 4 ones in the 48 or 64 pin package) can be used. All zeroes
is equivalent to 0x01.
0x01
15:8 CLKDIV
The VPB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D
converter, which should be less than or equal to 4.5 MHz. Typically, software should program
the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases
(such as a high-impedance analog source) a slower clock may be desirable.
0
16 BURST
If this bit is 0, conversions are software controlled and require 11 clocks. If this bit is 1, the AD
converter does repeated conversions at the rate selected by the CLKS field, scanning (if
necessary) through the pins selected by 1s in the SEL field. The first conversion after the start
corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if
applicable. Repeated conversions can be terminated by clearing this bit, but the conversion
that’s in progress when this bit is cleared will be completed..
0
19:17 CLKS
This field selects the number of clocks used for each conversion in Burst mode, and the
number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits)
and 4 clocks (3 bits): 000=11 clocks/10 bits, 001=10 clocks/9 bits,..., 111=4 clocks/3 bits
000
21 PDN
1: the A/D converter is operational
0: the A/D converter is in power down mode
0
23:22 TEST1:0
These bits are used in device testing. 00=normal operation, 01=digital test mode, 10=DAC
test mode, and 11=simple conversion test mode.
0
26:24 START
When the BURST bit is 0, these bits control whether and when an A/D conversion is started:
000: no start (this value should be used when clearing PDN to 0)
001: start conversion now
010: start conversion when the edge selected by bit 27 occurs on P0.16/EINT0/MAT0.2/
CAP0.2
011: start conversion when the edge selected by bit 27 occurs on P0.22/TD3/CAP0.0/MAT0.0
Note: for choices 100-111 the MAT signal need not be pinned out:
100: start conversion when the edge selected by bit 27 occurs on MAT0.1
101: start conversion when the edge selected by bit 27 occurs on MAT0.3
110: start conversion when the edge selected by bit 27 occurs on MAT1.0
111: start conversion when the edge selected by bit 27 occurs on MAT1.1
000
27 EDGE
This bit is significant only when the START field contains 010-111. In these cases:
0: start conversion on a falling edge on the selected CAP/MAT signal
1: start conversion on a rising edge on the selected CAP/MAT signal
0
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