13. Timer S
puorG92/C61M
page 143
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2110-1010B90JER
Figure 13.3 G1DV Register and G1BCR1 Register
Divider Register
Symbol Address After Reset
G1DV 032A
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
Function Setting range
Divide f
1, f2 or two-phase pulse input by (n+1)
for f
BT1 clock cycles generation.
n: the setting value of the G1DV register
0016 to FF16
RST1
0: The base timer is not reset by
applying "L" to the INT1 pin
1: The base timer is reset by applying "L"
to the INT1 pin
Base Timer Control Register 1
Symbol Address After Reset
G1BCR1 0323
16
00
16
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name Function
Bit
Symbol
b6
0
0
1
1
b5
0
1
0
1
(b0)
RST2
BTS
UD0
UD1
Base timer reset
cause select bit 1
Base timer reset
cause select bit 2
Counter increment/
decrement control bit
0: Base timer is reset
1: Base timer starts counting
: Counter increment mode
: Counter increment/decrement mode
: Two-phase pulse signal processing
mode
: Do not set to this value
NOTS:
1. The base timer is reset two f
BT1 clock cycles after the base timer matches the value set in the
G1PO0 register. (See Figure 13.7 for details on the G1PO0 register) When the RST1 bit is set to 1,
the value of the G1POj register (j=1 to 7) for the waveform generating function must be set to a
value smaller than that of the G1PO0 register.
When the RST1 bit is set to 1, set the RST4 bit in the G1BCR0 register to 0.
Reserved bit Set to 0
0: The base timer is not reset by
matching the G1PO0 register
1: The base timer is reset by matching
with the G1PO0 register
(1)
Reserved bit Set to 0
Reserved bit Set to 0
RW
(b3)
(b7)
Base timer start bit
0 00
b7 b6 b5 b4 b3 b2 b1 b0
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