14.Serial I/O
puorG92/C61M
page 184
854fo7002,03.raM21.1.veR
2110-1010B90JER
14.1.1.1 Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,
follow the procedures below.
•Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to 0 (reception disabled)
(2) Set bits SMD2 to SMD0 in the UiMR register to 0002 (Serial I/O disabled)
(3) Set bits SMD2 to SMD0 in the UiMR register to 0012 (Clock synchronous serial I/O mode)
(4) Set the RE bit in the UiC1 register to 1 (reception enabled)
•Resetting the UiTB register (i=0 to 2)
(1) Set bits SMD2 to SMD0 in the UiMR register to 0002 (Serial I/O disabled)
(2) Set bits SMD2 to SMD0 in the UiMR register to 0012 (Clock synchronous serial I/O mode)
(3) 1 is written to TE bit in the UiC1 register (reception enabled), regardless to the TE bit.
To Next Page
Loading...
