11-20 Testing and Troubleshooting Date Code 20010731
SEL-352-1, -2 Instruction Manual
element asserts, and set the SER to trigger for the TRIPA, 50FT, and FBF
elements. Verify the settings with the SHO command, and verify the SHO G
command for TRIPA.
Setting
Elements
FTLOG, 50FT,
FCpu, TRIPA
50FT, FBF
2. Connect an external timer, and set it to start when the TRIPA input asserts and
stop when the programmable output you set in Step 1 asserts.
3. Apply A-phase current above the 50FT setting. The relay should generate an
event report.
4. Assert the TRIPA input. This action causes the relay to start its 62FC timer. The
external timer should also start.
5. Shortly after the TRIPA input asserts, the programmable output contact set in
Step 1 should close, indicating FBF bit assertion. This action should stop the
external timer. Record the timer reading. It should be close to the FCpu setting.
6. Deassert the TRIPA input, and shut off A-phase current.
7. This step is optional. To test Scheme 3 logic operation under conditions that
could represent normal relay/breaker operation, repeat Steps 3 and 4. This time,
turn off A-phase current 1.5 to 2.0 cycles before the 62FC timer expires. The FBF
bit should not assert.
When Scheme 3 is enabled, the TRIP input is not latched. Thus, if TRIP input
deassertion occurs while phase current is applied but before 62FC timer
expiration, the relay does not assert the FBF bit.
8. Repeat Steps 3, 4, 5, 6, and 7 (optional) for phases B and C.
9. Set the external timer to start when you apply current to the relay and stop when
the programmable contact set in Step 1 closes.
10. Assert the TRIPA input.
11. Apply A-phase current above the 50FT setting. As a result, the relay starts its
62FC timer. The external timer should also start.
12. Shortly after you apply A-phase current, the programmable output contact set in
Step 1 should close, indicating FBF bit assertion. This action should stop the
external timer. Record the timer reading. It should be close to the FCpu setting.
13. Deassert the TRIPA input and shut off A-phase current.
14. This step is optional. To test Scheme 3 logic operation under conditions that
could represent normal relay/breaker operation, repeat Steps 10 and 11. This time,
turn off A-phase current 1.5 to 2.0 cycles before the 62FC timer expires. The FBF
bit should not assert.
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