3-22 Breaker Logic Date Code 20010731
SEL-352-1, -2 Instruction Manual
Ground Current Detector (50N)
Range: 0.10–45.00 A in 0.01-A steps (5 A)
0.02–9.00 A in 0.01-A steps (1 A)
The 50N ground current detector is not used in any of the default logic or scheme selections. It
is available for custom applications. The 50N setting is compared against a calculated 3•I0,
which is simply the vector sum of all three current inputs. Under balanced conditions, the result
of this calculation is zero. Consider normal system unbalance when using this element. Some
systems can have as much as 10 percent to 15 percent unbalance. As either load or the number
of faults increases, so does the amount of unbalance calculated.
Set the 50N so that it will not pick up for normal operating conditions because of system
unbalance. For detecting faults, a setting of 50 percent or less of the calculated ground current
provides margin for differences in ground impedance.
Load Current Logic Enable (LDLOG)
Range: OFF, 1, 2, CUSTOM
Use SET <ENTER> to access the LDLOG setting. Enable, modify, or disable load current
protection.
If you do not want load current protection, set LDLOG = OFF. If you need logic for your
application different from that available with either of the two schemes, set LDLOG =
CUSTOM. When CUSTOM is selected, all load current settings are shown including the
SEL
OGIC control equations. Modify these settings to meet your specific application needs.
Load Current Timers (LPpu, LDpu)–Schemes 1 and 2
Range: 0–16383 cycles in 1/4-cycle steps
Use SET <ENTER> to access the LPpu and LDpu timers. These are breaker pending failure
and failure timers, respectively, for the failure-to-trip load current breaker protection scheme.
The time delay of this protection scheme is typically set longer than fault current conditions due
to lower current duties associated with this type of breaker failure operation. Extending the time
delay allows more time for a slow but operative breaker to clear a low-current fault. A
disadvantage in the extended time delay is that a fault does remain on longer if the breaker
actually fails. You must weigh these considerations when selecting time delays for this scheme.
Please note that some breakers actually take more time to break low amounts of current. Consult
the manufacturer of the protected breaker for details.
The timing of this protection scheme is nearly identical to that of Scheme 2 of the fault current
logic shown in Figure 3.9. The difference is that pending failure bit LPF is provided with this
scheme. Consider using the LPF bit to retrip the protected breaker through a second trip coil.
The recommended setting for LDpu is the nominal breaker operate time, plus the 50FT dropout
time, plus a safety margin. Calculate the safety margin by subtracting all conditions required to
isolate the fault during a breaker failure condition from the maximum acceptable fault clearing
time. The safety margin will be longer in this case than for the fault current logic because the
total acceptable time to clear the fault at these lower fault duties is longer.
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