Schweitzer Engineering Laboratories SEL-352-1 - Pending Failure and Breaker Failure (Appu, Afpu)-Scheme 2; Setting Calculations; Pending Failure and Breaker Failure (Lppu, Ldpu)

Date Code 20010731 Breaker Logic 3-23
SEL-352-1, -2 Instruction Manual
The LPpu setting value is based on the breaker operate time and the time calculated for LDpu. If
using the LPpu to energize a second trip coil, the LPF bit should assert in enough time to let the
breaker operate before tripping the lockout relay with the LBF bit. The recommended setting for
LPpu is LDpu minus the nominal breaker operate time and some margin.
52A Pending Failure and Breaker Failure (APpu, AFpu)–Scheme 2
Range: 0–16383 cycles in 1/4-cycle steps
Use SET <ENTER> to access the APpu and AFpu timers. These are 52A supervised pending
failure and breaker failure timers, respectively, for the failure-to-trip load current breaker
protection scheme.
The time delay settings should be selected based on the maximum time permissible to operate
the protected equipment under low- or zero-current conditions. A slightly larger safety margin
should be considered for this logic than is allowed for the breaker failure timers described above.
The longer safety margin can allow for possible differences in expected and actual breaker
auxiliary contact operating times.
The recommended settings for APpu and AFpu are two cycles longer than the LPpu and LDpu
respectively. The two cycles allow for a slow 52A response time.
Setting Calculations
Pending Failure and Breaker Failure (LPpu, LDpu)
In our example application, Scheme 1 is selected because our conditions do not require the 52A
supervised breaker failure logic. Ten cycles are allowed to clear faults with current duties below
5456 A primary. Local and remote breaker operating times are considered identical to those
used in selecting the FCpu setting. Operating time of line protective relay Tpr is two cycles.
Specified reset time of the 50LD overcurrent element T50 is less than 1.55 cycles. Safety
margin time is defined as Ts and calculated below.
Ts = Tt – (Tpr + Tbl + T50 + Tbr +Tc) cycles
Ts = 10.0 – (2.0 + 2.0 + 1.55 + 2.0 + 0.5) cycles
Ts = 1.95 cycles
LDpu = Tbl + T50 + Ts = 5.5 cycles
We set the pending failure timer LPpu to retrip the protected breaker more than two cycles
before tripping the lockout relay:
LPpu = 3.25 cycles