Schweitzer Engineering Laboratories SEL-352-1 - Load Current Breaker Failure, Scheme 1 Logic Test

Date Code 20010731 Testing and Troubleshooting 11-23
SEL-352-1, -2 Instruction Manual
9. Repeat Steps 3, 4, 5, 6, and 7 (optional) for phases B and C.
10. For each test, the relay generated a sequential events record for the elements
programmed in Step 1. View the SER using the SER command. These time
stamps will also verify the FCpu setting. The FCpu timer is the time between the
assertion of TRIPA and assertion of FBF.
LOAD CURRENT BREAKER FAILURE, SCHEME 1 LOGIC TEST
Purpose: Verify operation of the Scheme 1 load current breaker failure logic (Reference:
Figure 3.17).
Method: 1. While the relay can use two different load current breaker failure schemes, only
one is enabled at a time. Select Scheme 1 by setting LDLOG = 1 in the relay
setting group. Using the SET command, set an output to close when the LBF
element asserts, and set the SER to trigger for the TRIPA, 50LD, LPF, and LBF
elements. Verify the settings with the SHO command, and verify the SHO G
command for TRIPA.
Setting
Elements
LDLOG, 50LD,
LPpu, LFpu
TRIPA
50FT, FBF
2. Connect an external timer, and set it to start when the TRIPA input asserts and
stop when the programmable output you set in Step 1 asserts.
3. Apply A-phase current above the 50LD setting. (Current should not exceed the
50FT setting.)
4. Assert the TRIPA input. This starts the relay 62LP and 62LD timers. The
external timer should also start.
5. Shortly after TRIPA input assertion, the programmable output contact set in Step
1 should close, indicating LBF bit assertion. This action should stop the external
timer. Record the timer reading. It should be close to the LDpu setting.
6. Deassert the TRIPA input, and shut off A-phase current.
7. This step is optional. To test logic operation under conditions that could represent
normal relay/breaker operation, repeat Steps 3 and 4. This time, turn off A-phase
current 1.5 to 2.0 cycles before the 62LD timer expires. The LBF bit should not
assert.
8. Repeat Steps 3, 4, 5, 6, and 7 (optional) for phases B and C.
9. In Step 5, 62LP timer expiration can generate an event report. You can set the
LPF bit in a programmable output contact mask, and perform Steps 3, 4, 5, 6, and
7 to test the load current pending failure logic.
10. For each test, the relay generated a sequential events record for the elements