Schweitzer Engineering Laboratories SEL-352-1 - Load Current Breaker Failure, Scheme 2 Logic Test

11-24 Testing and Troubleshooting Date Code 20010731
SEL-352-1, -2 Instruction Manual
programmed in Step 1. View the SER using the SER command. These time
stamps will also verify the LPpu and LFpu timers. The LPpu and LFpu times are
the times between the assertion of TRIPA and the assertion of LPF and LBF,
respectively.
LOAD CURRENT BREAKER FAILURE, SCHEME 2 LOGIC TEST
Purpose: Verify operation of the Scheme 2 load current breaker failure logic (Reference:
Figure 3.18).
Method: 1. While the relay can use two different load current breaker failure schemes, only
one is enabled at a time. Select Scheme 2 by setting LDLOG = 2 in the relay
setting group. Scheme 2 includes all of Scheme 2 logic plus additional logic that
monitors the breaker status. Perform Scheme 1 testing in addition to the following
tests. Using the SET command, set an output to close when the LBF element
asserts, and set the SER to trigger for the TRIPA, 52AA, LPF, and LBF elements.
Verify the settings with the SHO command, and verify the SHO G command for
TRIPA and 52AA.
Setting
Elements
LDLOG, APpu,
AFpu TRIPA,
52A
50FT, FBF
2. Connect an external timer, and set it to start when the TRIPA input asserts and
stop when the programmable output you set in Step 1 asserts.
3. Assert the 52AA input.
4. Assert the TRIPA input. This starts the relay 62AP and 62AF timers. The
external timer should also start.
5. Shortly after TRIPA input assertion, the programmable output contact set in
Step 1 should close, indicating LBF bit assertion. This action should stop the
external timer. Record the timer reading. It should be close to the LDpu setting.
6. Deassert the TRIPA and 52AA inputs.
7. This step is optional. To test logic operation under conditions that could represent
normal relay/breaker operation, repeat Steps 3 and 4. This time, deassert the
52AA input 1.5 to 2.0 cycles before the 62AF timer expires. The LBF bit should
not assert.
8. Repeat Steps 3, 4, 5, 6, and 7 (optional) for phases B and C.
9. In Step 5, 62LP timer expiration can generate an event report. You can set the
LPF bit in a programmable output contact and perform Steps 3, 4, 5, 6, and 7 to
test the load current pending failure logic.
10. For each test, the relay generated a sequential events record for the elements
programmed in Step 1. View the SER using the SER command. These time