Date Code 20010731 Testing and Troubleshooting 11-21
SEL-352-1, -2 Instruction Manual
When Scheme 3 is enabled, the TRIPA input is not latched. Thus, if the TRIPA
input deasserts while phase current is applied but before 62FC timer expiration,
the relay does not assert the FBF bit.
15. Repeat Steps 10, 11, 12, 13, and 14 (optional) for phases B and C.
16. For each test, the relay generated a sequential events record for the elements
programmed in Step 1. View the SER using the SER command. These time
stamps will also verify the FCpu timer. The FCpu time is the time between the
assertion of TRIPA and the assertion of FBF.
FAULT CURRENT BREAKER FAILURE, SCHEME 4 LOGIC TEST
Purpose: Verify operation of the Scheme 4 fault current breaker failure logic (Reference:
Figure 3.12).
Method: 1. While the relay can use five different fault current breaker failure schemes, only
one is enabled at a time. Select Scheme 4 by setting FTLOG = 4 in the relay
setting group. Using the SET command, set an output to close when the FBF
element asserts, and set the SER to trigger for the TRIPA, 50FT, and FBF
elements. Verify the settings with the SHO command, and verify the SHO G
command for TRIPA.
Setting
Elements
FTLOG, 50FT,
TTpu, TTdo
TRIPA
50FT, FBF
2. Connect an external timer and set it to start when the TRIPA input asserts and stop
when the programmable output you set in Step 1 asserts.
3. Apply A-phase current above the 50FT setting. The relay should generate an
event report.
4. Assert the TRIPA input. This action causes the relay to start its 62TT timer. The
external timer should also start.
5. Shortly after the TRIPA input asserts, the programmable output contact set in
Step 1 should close, indicating FBF bit assertion. This action should stop the
external timer. Record the timer reading. It should be close to the TTpu setting.
6. Deassert the TRIPA input and shut off A-phase current.
7. This step is optional. To test Scheme 4 logic operation under conditions that
could represent normal relay/breaker operation, repeat Steps 3 and 4. This time,
turn off A-phase current 1.5 to 2.0 cycles before the 62TT timer expires. The FBF
bit should not assert.
8. Repeat Steps 3, 4, 5, 6, and 7 (optional) for phases B and C.
9. Assert the TRIPA input. Apply A-phase current TTpu cycles following TRIPA
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