Schweitzer Engineering Laboratories SEL-352-1 - Scheme 2 (Fault Current)

3-10 Breaker Logic Date Code 20010731
SEL-352-1, -2 Instruction Manual
Scheme 2 (Fault Current)
Scheme 2 (FTLOG=2) provides breaker failure protection logic for single-breaker applications.
It may also be used for multiple-breaker applications where sequential/delayed tripping is
acceptable due to current distribution. This scheme adds a set/reset latch to the Scheme 3 logic
to allow for a pulsed trip input. LFA latches when TRIPA and 50FTA are both asserted for a
quarter-cycle. It resets when 50FTA deaaserts. The 62FC timer starts after LFA is set and
continues to time until 50FT resets LFA or FCpu times out.
The logic shown in Figure 3.8 protects the system from a breaker failure during a fault. This
scheme is applicable to single breaker configurations. In a single breaker arrangement, fault
current causes the 50FTA element to assert immediately following fault inception and just prior
to TRIPA input assertion. If 50FTA is asserted when the relay receives the TRIPA input, the
62FC timer starts and latches. At this point, trip signal dropout does not affect the breaker
failure scheme. If the 50FTA element remains asserted until the 62FC timer expires, the Relay
Word FBF bit asserts. If the breaker operates successfully, the 50FTA element drops out before
the 62FC timer expires, and FBF does not assert.
Although it is very simple and effective in single breaker arrangements, Scheme 2 is not
recommended when the protected breaker is part of a ring-bus or breaker-and-a-half installation.
Consider using Scheme 1, Scheme 4, or Scheme 5 in such breaker arrangements.
Figure 3.8: A-Phase Failure to Trip for Fault Logic, Scheme 2
Figure 3.9 depicts the breaker failure condition that results when 62FC times out.