Date Code 20010731 Testing and Troubleshooting 11-37
SEL-352-1, -2 Instruction Manual
INSTANTANEOUS RETRIP, SCHEME 1 RETRIP LOGIC TEST
Purpose: Verify Scheme 1 of the retrip logic.
Method: 1. While the relay can use two different retrip schemes, only one is enabled at a time.
Select Scheme 1 by setting RTPLOG = 1 in the relay setting group. Using the
SET command, set an output to close when the RTA element asserts, and set the
SER to trigger for the listed elements. Verify the TRIPA setting with the SHO G
command.
Setting
Elements
RTPLOG,
TRIPA
RTA, TRIPA
2. Assert the TRIPA input by applying dc control voltage to the assigned input
terminals. Verify that the output contact set in Step 1 closes.
3. For each test, the relay generated a sequential events record for the elements
programmed in Step 1. View the SER using the SER command. Observe the
assertion of TRIPA and RTA.
4. Repeat Steps 2 and 3 for each phase.
TIME-DELAYED RETRIP, SCHEME 2 RETRIP LOGIC TEST
Purpose: Verify Scheme 2 of the retrip logic (Reference: Figure 4.11 Retrip logic diagram).
Method: 1. While the relay can use two different retrip schemes, only one is enabled at a time.
Select Scheme 2 by setting RTPLOG = 2 in the relay setting group. Using the
SET command, set an output to close when the RTA element asserts, and set the
SER to trigger for the listed elements. Verify the TRIPA setting with the SHO G
command.
Setting
Elements
RTPLOG,
TRIPA
RTA, TRIPA
2. Connect an external timer, and set it to start when you assert the TRIPA input and
stop when the programmable output you set in Step 1 asserts.
3. Apply balanced three-phase current above the 50LD setting. Assert the TRIPA
input by applying dc control voltage to the TRIPA input terminals. This should
start the external timer.
4. A moment later, the output contact you set in Step 1 should close, stopping the
external timer. Take note of the time recorded. It should be approximately equal
to the RTpu timer setting.
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