Schweitzer Engineering Laboratories SEL-387E - SET Menu

3-40 Protection Functions Date Code 20080110
SEL-387E Instruction Manual
51Qn Negative-Sequence Inverse-Time Element
The 51Q n element logic compares the magnitude of the calculated negative-sequence current,
3I2W
n , to the pickup setting, 51Q n P. If the calculated negative-sequence current exceeds the
pickup level, a logical 1 asserts at one input to the AND gate at the center. The torque-control
SEL
OGIC control equation, 51Q n TC, determines the other AND input. If 51Q n TC is true, Relay
Word bit 51P
n asserts and the inverse curve begins timing.
As with phase inverse-time element logic, four settings define the curve. In this case 51Q
n P is
the pickup, 51Q
n C defines the curve equation, 51Q n TD defines the time dial, and 51Q n RS
determines how the curve resets.
Curve time-out causes Relay Word bit 51Q
n T to assert. When the current drops below pickup,
51Q
n deasserts and the element resets according to the setting for 51Q n RS. At the completion of
the reset, Relay Word bit 51Q
n R asserts. This bit normally is at logic state 1, when the element is
at rest during normal system operation. You can use the
TAR command to verify the state of the
bit. You can use the Level 2 serial port command
RES or the front-panel RESET51 function
under the OTHER button to force the bit to a logical 1 during element testing. This saves time if
you have chosen electromechanical reset.
51Nn Residual Inverse-Time Element
The 51N n element compares the magnitude of the calculated residual current, IRW n , to the
pickup setting, 51N
n P. If calculated residual current exceeds the pickup level, a logical 1 asserts
at one input to the AND gate at the center. The torque-control SEL
OGIC control equation,
51N
n TC, determines the other AND input. If 51N n TC is true, Relay Word bit 51N n asserts and
the inverse curve begins timing.
The settings defining the curve in this case are 51N
n P for the pickup setting, 51N n C for the
particular curve equation, 51N
n TD for the time dial, and 51N n RS for the curve reset.
Curve time-out causes Relay Word bit 51N
n T to assert. When the current drops below pickup,
51N
n deasserts and the element resets according to the setting for 51N n RS. At the completion of
the reset, Relay Word bit 51N
n R asserts. This bit normally is at logic state 1, when the element is
at rest during normal system operation. You can use the
TAR command to verify the state of the
bit. You can use the Level 2 serial port command
RES or the front-panel RESET51 function
under the OTHER button to force the bit to a logical 1 during element testing.
51PC1 and 51NC1 Combined Overcurrent Elements
The combined overcurrent elements operate on summed input currents to two windings.
Elements 51PC1 and 51NC1 use phase and residual current from Windings 1 and 2. See
Figure
3.22.