Chapter 11 Power-On Self-Test 11-7
0>CPU Tick and Tick Compare Registers Test
Operation of TICK registers is
verified.
0>CPU Stick and Stick Compare Registers Test
Operation of STICK registers is
verified.
0>Set Timing
Motherboard timing is to be
configured.
0> UltraSPARC[TM] IIIi, Version 3.4
CPU version is identified.
0>Interrupt Crosscall.....
0>Setup Int Handlers
Interrupt handlers are set up.
0>MB: Part-Dash-Rev#: 3753279-02-0C Serial#:
000225
Motherboard part number and
serial number is read from FRU
ID.
0>CPU0 DIMM 0:
0>Part#: 18VDDF12872Y-335D3 Serial#: 71fe1ec9 Date
Code: 0506 Rev#: 0300
0>CPU0 DIMM 1:
0>Part#: 18VDDF12872Y-335D3 Serial#: 71fe1e32 Date
Code: 0506 Rev#: 0300
DIMM part numbers, serial
numbers, date codes, and
revisions are read from the
DIMM’s internal firmware.
0>Set CPU/System Speed
0>MCR Timing index = 00000000.00000007
0>..
Jumpers for CPU and JBus
frequency are read.
0>Init Memory.....
Memory is initialized.
0>Probe Dimms
Presence of DIMMs is checked.
0>Init Mem Controller Regs
Memory controller registers are
initialized.
0>Set JBUS config reg
JBus configuration register is set.
0>IO-Bridge unit 1 init test
0>Clear TLU loopback for PCI-E
I/O bridge chip is initialized.
0>Do PLL reset
0>Setting timing to 8:1 12:1, system frequency 200
MHz, CPU frequency 1600 MHz
Phase-locked loop (PLL) is reset
for the selected frequencies.
ø0>Soft Power-on RST thru SW
Soft reset.
TABLE 11-6 post max max Output Comparison (Continued)
Output Displayed What Is Happening
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