Sun Microsystems Ultra 25 - Page 138

11-8 Sun Ultra 45 and Ultra 25 Workstations Service and Diagnostics Manual • May 2006
0>PLL Reset.....
0>Initialize I2C Controller
0>Init CPU
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0> Size = 00000000.00100000...
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Scrub Mailbox
Initializations and setups are
repeated.
0>Timing is 8:1 12:1, sys 200 MHz, CPU 1600 MHz, mem
133 MHz.
New timing ratios and frequencies
are displayed.
0> UltraSPARC[TM] IIIi, Version 3.4
0>Init Memory.....
0>Probe Dimms
0>Init Mem Controller Sequence
0>Clear TLU loopback for PCI-E
Repeated initialization continues.
0>Test Memory.....
0>Select Bank Config
0>Probe and Setup Memory
0>INFO: 2048MB Bank 0, Dimm Type X4
0>INFO: No memory detected in Bank 1
0>INFO: No memory detected in Bank 2
0>INFO: No memory detected in Bank 3
0>
0>Test Memory.....
0>Select Bank Config
0>Probe and Setup Memory
0>INFO: 2048MB Bank 0, Dimm Type X4
0>INFO: No memory detected in Bank 1
0>INFO: No memory detected in Bank 2
0>INFO: No memory detected in Bank 3
0>
Memory is probed.
0>Data Bitwalk on Master
CPU data pins are tested.
0> Test Bank 0.
Where found, memory is tested.
0>Address Bitwalk on Master
0>Addr walk mem test on CPU 0 Bank 0:
00000000.00000000 to 00000000.80000000.
CPU address pins are tested.
0>Set Mailbox
Mailbox region is set in memory.
0>Final mc1 is 1000000a.1e581c61
Memory control register1 is set.
TABLE 11-6 post max max Output Comparison (Continued)
Output Displayed What Is Happening