Xilinx Virtex-5 RocketIO GTP

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 25
UG196 (v1.3) May 25, 2007
Ports and Attributes
R
INTDATAWIDTH In Async
Sets the internal datapath width for the
GTP_DUAL tile.
0: 8-bit internal datapath width
1: 10-bit internal datapath width
Shared PMA PLL
(page 61), FPGA TX
Interface (page 90),
Parallel In to Serial Out
(PISO) (page 110),
Configurable RX Elastic
Buffer and Phase
Alignment (page 162),
Configurable Clock
Correction (page 169),
Configurable Channel
Bonding (Lane Deskew)
(page 176), FPGA RX
Interface (page 182)
LOOPBACK0[2:0]
LOOPBACK1[2:0]
In Async Sets the loopback mode. Loopback (page 196)
PHYSTATUS0
PHYSTATUS1
Out Async
Indicates completion of several PHY
functions, including power
management state transitions and
receiver detection.
PCI Express Receive
Detect Support
(page 116)
PLLLKDET Out Async
Indicates that the VCO rate is within
acceptable tolerances of the desired
rate.
Shared PMA PLL
(page 61)
PLLLKDETEN In Async Enables the PLL lock detector.
Shared PMA PLL
(page 61)
PLLPOWERDOWN In Async Powers down the shared PMA PLL. Power Control (page 81)
PRBSCNTRESET0
PRBSCNTRESET1
In RXUSRCLK2 Resets the PRBS error counter.
PRBS Detection
(page 147)
REFCLKOUT Out N/A
Provides access to the reference clock
provided to the shared PLL (CLKIN).
Shared PMA PLL
(page 61), Clocking
(page 70), FPGA TX
Interface (page 90), TX
Buffering, Phase
Alignment, and Buffer
Bypass (page 104),
FPGA RX Interface
(page 182)
REFCLKPWRDNB In Async
Powers down the GTP reference clock
circuit (active Low).
Power Control (page 81)
RESETDONE0
RESETDONE1
Out Async
Indicates when the GTP transceiver has
finished reset and is ready for use.
Reset (page 73), RX
Clock Data Recovery
(CDR) (page 136)
Table 1-3: GTP_DUAL Port Summary (Continued)
Port Dir Domain Description Section (Page)