Xilinx Virtex-5 RocketIO GTP

UG196 (v1.3) May 25, 2007 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
05/25/07 1.3 Chapter 1: Revised line rates in the “Overview,” page 19. Added to RXBYTEISALIGNED
description and removed CRC ports in Table 1-3, page 24. Corrected
PCOMMA_DETECT entry and removed CRC_INIT[31:0] attribute in Table 1-4. CRC
ports are not part of the GTP_DUAL primitive. See Chapter 8.
Chapter 3: Added “Providing Clocks In Simulation,” page 44. Added multirate clocking
design caveats and link to Appendix F.
Chapter 4: Added a note 2 to Table 4-1, page 49.
Chapter 5: Added to note 5 in Figure 5-1, page 60. Added PCS_COM_CFG and notes to
Figure 5-2, page 63. Revised Equation 5-1. Changed PLL clock frequency for FC1, FC2,
SFI-5, TFI-5, and the HD-SDI standard in Table 5-3, page 63. Revised the notes for
Figure 5-5, page 71. Added PRBSCNTRESET and PLLPOWERDOWN, and revised
GTPRESET description in Table 5-6, page 73. Revised “GTP Component-Level Resets”
and “Link Idle Reset Support,” page 75. Added note to RXPOWERDOWN in Table 5-9,
page 81. Added note to Table 5-11, page 83.
Chapter 6: Added a BUFG to Figure 6-5. Revised PMA_COM_CFG,
OVERSAMPLE_MODE, and added three attributes to Table 6-8, page 105. Revised the
“Using the TX Phase-Alignment Circuit to Bypass the TX Buffer,” page 106. Revised
Figure 6-12, page 107. Added INTDATAWIDTH to Table 6-12, page 109. Revised
OVERSAMPLE_MODE in Table 6-14, page 111. Revised TX_DIFF_BOOST in Table 6-16,
page 113. Added default value to Table 6-18, page 114.
Chapter 7: Revised Figure 7-2, page 126. Updated Table 7-3. Added OOB nominal values
to Table 7-6. Added “Tuning the CDR,” page 139. Revised Table 7-12, page 141. Added
note 1 to Table 7-29, page 163. Revised CLK_COR_MAX_LAT
Chapter 8: Added clarification to the CRC block description.
Chapter 9: Made changes to “Near-End PCS Loopback,” “Near-End PMA Loopback,”
“Far-End PMA Loopback,” and “Far-End PCS Loopback,” including adding “Marginal
Conditions and Limitations.” Added Table 9-2.
Chapter 10: Clarified
“REFCLK Guidelines,” page 207. Added Figure 10-9. Added
TERMINATION_IMP to Table 10-2. Added note on analog supplies to Table 10-3,
Table 10-4, and Table 10-5. Added SelectIO Adjacent to MGTCLK tables at the end of the
chapter. Edited “AC Coupling,” page 210. Added an additional guideline to “Filter
Network Design Guidelines.”
Appendix D: Added PCS_COM_CFG to Table D-2, Table D-7, and Table D-8. Revised bit
4 and 6 in Table D-3.
Appendix E: Added note 2 to Table E-2, page 311.
Added Appendix F.
Date Version Revision