Xilinx Virtex-5 RocketIO GTP User Manual

56 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 4: Implementation
R
Figure 4-5: XC5VLX110T-FF1738, XC5VLX220T-FF1738, and XC5VLX330T-FF1738 GTP Placement (1 of 3)
H3
MGTAVCCPLL_128D10 MGTREFCLKP_128
XC5VLX110T: Not Available
XC5VLX220T: Not Available
XC5VLX330T: GTP_DUAL_X0Y10
C10 MGTREFCLKN_128
G3
MGTAVCC_128
G4
MGTAVCC_128
A8 MGTRXP1_128
A9 MGTRXN1_128
E3
MGTAVTTRX_128A11 MGTRXP0_128
A10 MGTRXN0_128
D3
MGTAVTTTX_128
J3
MGTAVTTTX_128
B7 MGTTXP1_128
B8 MGTTXN1_128
B12 MGTTXP0_128
B11 MGTTXN0_128
C2
MGTAVCCPLL_132D16 MGTREFCLKP_132
Power PinsRight Edge of the Die
XC5VLX110T: Not Available
XC5VLX220T: Not Available
XC5VLX330T: GTP_DUAL_X0Y11
C16 MGTREFCLKN_132
D4
C15
MGTAVCC_132
D5
MGTAVCC_132
A14 MGTRXP1_132
A15 MGTRXN1_132
C5
MGTAVTTRX_132A17 MGTRXP0_132
A16 MGTRXN0_132
C1
MGTAVTTTX_132
C6
C8
C9
D9
C11
C12
C7
C14
D15
C17
C13
C18
MGTAVTTTX_132
B13 MGTTXP1_132
B14 MGTTXN1_132
B18 MGTTXP0_132
B17
F4
F3
H1
G1
E1
F1
J2
H2
D2
E2
C4
C3
A2
A3
A5
A4
B1
B2
B6
B5
MGTTXN0_132
MGTAVCCPLL_120MGTREFCLKP_120
MGTREFCLKN_120
MGTAVCC_120
MGTAVCC_120
MGTRXP1_120
MGTRXN1_120
MGTAVTTRX_120MGTRXP0_120
MGTRXN0_120
MGTAVTTTX_120
MGTAVTTTX_120
MGTTXP1_120
MGTTXN1_120
MGTTXP0_120
MGTTXN0_120
MGTAVCCPLL_124MGTREFCLKP_124
MGTREFCLKN_124
MGTAVCC_124
MGTAVCC_124
MGTRXP1_124
MGTRXN1_124
MGTAVTTRX_124MGTRXP0_124
MGTRXN
0_124
MGTAVTTTX_124
MGTAVTTTX_124
MGTTXP1_124
MGTTXN1_124
MGTTXP0_124
MGTTXN0_124
XC5VLX110T: GTP_DUAL_X0Y7
XC5VLX220T: GTP_DUAL_X0Y7
XC5VLX330T: GTP_DUAL_X0Y9
XC5VLX110T: GTP_DUAL_X0Y6
XC5VLX220T: GTP_DUAL_X0Y6
XC5VLX330T: GTP_DUAL_X0Y8
UG196_c4_05_110906

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English