Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 57
UG196 (v1.3) May 25, 2007
Package Placement Information
R
Figure 4-6: XC5VLX110T-FF1738, XC5VLX220T-FF1738, and XC5VLX330T-FF1738 GTP Placement (2 of 3)
XC5VLX110T: GTP_DUAL_X0Y4
XC5VLX220T: GTP_DUAL_X0Y4
XC5VLX330T: GTP_DUAL_X0Y6
Power PinsRight Edge of the Die
XC5VLX110T: GTP_DUAL_X0Y5
XC5VLX220T: GTP_DUAL_X0Y5
XC5VLX330T: GTP_DUAL_X0Y7
P3 MGTAVCCPLL_116M4 MGTREFCLKP_116
XC5VLX110T: GTP_DUAL_X0Y3
XC5VLX220T: GTP_DUAL_X0Y3
XC5VLX330T: GTP_DUAL_X0Y5
M3 MGTREFCLKN_116
N3MGTAVCC_116
N4MGTAVCC_116
P1 MGTRXP1_116
N1 MGTRXN1_116
L3 MGTAVTTRX_116L1 MGTRXP0_116
M1 MGTRXN0_116
R3 MGTAVTTTX_116
K3 MGTAVTTTX_116
R2 MGTTXP1_116
P2 MGTTXN1_116
K2 MGTTXP0_116
L2 MGTTXN0_116
Y3 MGTAVCCPLL_112V4 MGTREFCLKP_112
XC5VLX110T: GTP_DUAL_X0Y2
XC5VLX220T: GTP_DUAL_X0Y2
XC5VLX330T: GTP_DUAL_X0Y4
V3 MGTREFCLKN_112
W3MGTAVCC_112
W4MGTAVCC_112
Y1 MGTRXP1_112
W1 MGTRXN1_112
U3 MGTAVTTRX_112U1 MGTRXP0_112
V1 MGTRXN
0_112
AA3 MGTAVTTTX_112
T3 MGTAVTTTX_112
AA2 MGTTXP1_112
Y2 MGTTXN1_112
T2 MGTTXP0_112
U2 MGTTXN0_112
UG196_c4_06_110906
AM3 MGTAVCCPLL_118AK4 MGTREFCLKP_118
AK3 MGTREFCLKN_118
AL3 MGTAVCC_118
AL4 MGTAVCC_118
AM1 MGTRXP1_118
AL1 MGTRXN1_118
AJ3 MGTAVTTRX_118AJ1 MGTRXP0_118
AK1 MGTRXN0_118
AH3 MGTAVTTTX_118
AN3MGTAVTTTX_118
AN2 MGTTXP1_118
AM2 MGTTXN1_118
AH2 MGTTXP0_118
AJ2 MGTTXN0_118
AF3 MGTAVCCPLL_114AD4 MGTREFCLKP_114
AD3 MGTREFCLKN_114
AE3 MGTAVCC_114
AE4 MGTAVCC_114
AF1 MGTRXP1_114
AE1 MGTRXN1_114
AC3 MGTAVTTRX_114AC1 MGTRXP0_114
AD1 MGTRXN0_114
AB3 MGTAVTTTX_114
AG3 MGTAVTTTX_114
AG2 MGTTXP1_114
AF2 MGTTXN1_114
AB2 MGTTXP0_114
AC2 MGTTXN0_114

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English