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ABOV Semiconductor Co., Ltd.
USTST (USART Status Register) : DCH
Initial value : 80H
The DRE flag indicates if the transmit buffer (USTDR) is ready to receive new data. If
DRE is ‘1’, the buffer is empty and ready to be written. The flag can generate a DRE
interrupt.
Transmit buffer is not empty.
Transmit buffer is empty.
This flag is set when the entire frame in the transmit shift register has been shifted out
and there is no new data currently present in the transmit buffer. This flag is
automatically cleared when the interrupt service routine of a TXC interrupt is executed.
This flag can generate a TXC interrupt.
Transmit buffer is empty and the data in transmit shift register are shifted out
completely.
This flag is set when there are unread data in the receive buffer and cleared when all
the data in the receive buffer are read. The RXC flag can be used to generate a RXC
interrupt.
There is no data unread in the receive buffer
There are more than 1 data in the receive buffer
This flag is set when the RXD pin is detected low while the CPU is in STOP mode. This
flag can be used to generate a WAKE interrupt (only UART mode)
No WAKE interrupt is generated.
WAKE interrupt is generated.
This is an internal reset and only has effect on USART. Writing ‘1’ to this bit initializes
the internal logic of USART and is automatically cleared to ‘0’.
This bit is set if data OverRun occurs. While this bit is set, the incoming data frame is
ignored. This flag is valid until the receive buffer is read.
This bit is set if the first stop bit of next character in the receive buffer is detected as ‘0’.
This bit is valid until the receive buffer is read (only UART mode)
This bit is set if the next character in the receive buffer has a Parity Error while Parity
Checking is enabled. This bit is valid until the receive buffer is read (only UART mode)
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