Abov MC96F8204 Series User Manual

138
MC96F8204
ABOV Semiconductor Co., Ltd.
USTCR3 (USART Control Register 3) : DBH
7
6
5
4
3
2
1
0
MASTER
LOOPS
DISSCK
USTSSEN
FXCH
USTSB
USTTX8
USTRX8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Initial value : 00H
MASTER
Selects master or slave in SPI or Synchronous mode operation and controls the
direction of SCK pin.
0
Slave operation (External clock for SCK)
1
Master operation (Internal clock for SCK)
LOOPS
Control the Loop Back mode of USART for test mode
0
Normal operation
1
Loop Back mode
DISSCK
In synchronous mode operation, selects the waveform of SCK output.
0
SCK is free-running while UART is enabled in synchronous master mode
1
SCK is active while any frame is on transferring
USTSSEN
This bit controls the SS pin operation (only SPI mode)
0
Disable
1
Enable (The SS pin should be a normal input)
FXCH
SPI port function exchange control bit (only SPI mode)
0
No effect
1
Exchange MOSI and MISO function
USTSB
Selects the length of stop bit in Asynchronous or Synchronous mode of operation.
0
1 Stop Bit
1
2 Stop Bit
USTTX8
The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write
this bit first before loading the USTDR register.
0
MSB (9
th
bit) to be transmitted is ‘0’
1
MSB (9
th
bit) to be transmitted is ‘1’
USTRX8
The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read
this bit first before reading the receive buffer (only UART mode)
0
MSB (9
th
bit) received is ‘0’
1
MSB (9
th
bit) received is ‘1’

Abov MC96F8204 Series Specifications

General

Brand	Abov
Model	MC96F8204 Series
Category	Microcontrollers
Language	English