Abov MC96F8204 Series

137
MC96F8204
ABOV Semiconductor Co., Ltd.
USTCR2 (USART Control Register 2) : DAH
7
6
5
4
3
2
1
0
DRIE
TXCIE
RXCIE
WAKEIE
TXE
RXE
USTEN
DBLS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
URIE
Interrupt enable bit for Data Register
0
Interrupt from DRE is inhibited (use polling)
1
When DRE is set, request an interrupt
TXCIE
Interrupt enable bit for Transmit Complete
0
Interrupt from TXC is inhibited (use polling)
1
When TXC is set, request an interrupt
RXCIE
Interrupt enable bit for Receive Complete
0
Interrupt from RXC is inhibited (use polling)
1
When RXC is set, request an interrupt
WAKEIE
Interrupt enable bit for Asynchronous Wake in STOP mode. When device is in stop
mode, if RXD goes to Low level, an interrupt can be requested to wake-up system (only
UART mode)
0
Interrupt from Wake is inhibited
1
When WAKE is set, request an interrupt
TXE
Enables the Transmitter unit
0
Transmitter is disabled
1
Transmitter is enabled
RXE
Enables the receiver unit
0
Receiver is disabled
1
Receiver is enabled
USTEN
Activate USART Function Block by supplying.
0
USART is disabled (clock is halted)
1
USART is enabled
DBLS
This bit selects receiver sampling rate (only UART mode)
0
Normal Asynchronous operation
1
Double Speed Asynchronous operation