Abov MC96F8204 Series User Manual

154
MC96F8204
ABOV Semiconductor Co., Ltd.
I2CCR (I2C Control Register) : E9H
7
6
5
4
3
2
1
0
IICRST
IICEN
TXDLYENB
IICIE
ACKEN
IMASTER
STOPC
STARTC
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Initial value : 00H
IICRST
Initialize Internal Registers of I2C.
0
No effect
1
Initialize I2C, auto cleared
IICEN
Activate I2C Function Block by Supplying.
0
I2C is disabled
1
I2C is enabled
TXDLYENB
I2CSDHR register control bit
0
Enable I2CSDHR register
1
Disable I2CSDHR register
IICIE
Interrupt Enable bit
0
Interrupt from I2C is inhibited (use polling)
1
Enable interrupt for I2C
ACKEN
Controls ACK signal Generation at ninth SCL period.
0
No ACK signal is generated (SDA = 1)
1
ACK signal is generated (SDA = 0)
NOTE) ACK signal is output (SDA =0) for the following 3 cases.
1. When received address packet equals to I2CSLA bits in I2CSAR.
2. When received address packet equals to value 0x00 with GCALL
enabled.
3. When I2C operates as a receiver (master or slave)
IMASTER
Represent operating mode of I2C
0
I2C is in slave mode
1
I2C is in master mode
STOPC
When I2C is master, STOP condition generation
0
No effect
1
STOP condition is to be generated
STARTC
When I2C is master, START condition generation
0
No effect
1
START or repeated START condition is to be generated
NOTE)
1. Refer to the external interrupt flag register (EIFLAG) for the I2C interrupt flags.

Abov MC96F8204 Series Specifications

General

Brand	Abov
Model	MC96F8204 Series
Category	Microcontrollers
Language	English